Digital VLSI Design

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Digital VLSI Design

• Full Automation
• Maximum benefit of scaling
• High speed ,low power

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MOS
CONSTANT
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Design metrics
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Long Channel Vs. Short Channel
SAME
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Long Channel Vs. Short ChannelId vs Vgs
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Sub-threshold operation
Required----
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INVERTER

• STATIC CHARACTERISTICS

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VTC DESIGN ISSUES

• STATIC POWER CONSUMPTION
• FULL LOGIC LEVELS
• SHARP TRANSITION
• SWITCHING THRESHOLD? NOISE MARGINS

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PRACTICAL VTC
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FIVE CRITICAL VOLTAGES
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SWITCHING THRESHOLD

• Vth
• Output changes its state

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Noise Margins
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ImplementationResistive load
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Design for Vol
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SAT. ENHANCEMENT LOAD INV.
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LIN. ENHANCEMENT LOAD INV.
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Static characteristics
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Operating regions
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VOH
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VOL
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VIL
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VIH
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V th
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Variation in Vth. by (w/L)
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Critical voltage

• Nothing
• We can design for wide noise margins
• Set Vth ½Vdd

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Why design for Vth? ½Vdd?
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Effect on kR
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Switching characteristics
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Delay calculationmethod 1
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CMOS Inverter Driving a Lumped Capacitance Load

• CMOS Inverter can be viewed as a single
  transistor either charging the Cload or
  discharging the Cload
• Vin is assumed to switch abruptly
• If Vin switches high, the NMOS Tx discharges
  Cload while the PMOS Tx turns OFF
• If Vin switches low, the PMOS Tx charges Cload
  while the NMOS Tx turns OFF
• Cload is comprised of
• Cgate due to the gate capacitance of receiving
  circuits
• Cwire of the interconnect metal
• Cparasitics of the inverter output junctions

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Switch Model of CMOS TransistorMODEL-1
Approximate as a simple RC network where R is
given as an equivalent resistance of the NMOS and
PMOS devices and C is given as the total lumped
Cload capacitance
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CMOS Inverter Transient ResponseSwitch model
Vout VDD (1 e t / RONCL )
Vout VDD (e t / RONCL )
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In velocity saturated device
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Method 2
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CMOS Inverter Propagation Delay(AVERAGE CURRENT
THROUGH LOAD)
V
DD
-VDD)
t
C
(V
pHL
L
50
I
av
V
out
I
tpLH C L (V50-VOL)
C
L
av
Iav
V
V
in
DD
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• WHERE
• Iav, HL ½ic(VINVOH, VOUT VOH) ic(VINVOH,
  VOUT V50)
• Iav, LH ½ic(VINVOL, VOUT V50)
  ic(VINVOL, VOUT VOL)
• SIMPLE
• neglects variation of cap. during the entire
  transition

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Method-3
Differential equation approach accurate
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tpHL
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tpLH
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Impact of Rise Time on Delay
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DELAY REDUCTION
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Delay as a function of VDD(?)
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Delay as a function of CL(?)DELAY a CLDelay
as a function of W/L(?)DELAY a (W/L)-1
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MINIMUM POSSIBLE DELAY
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Computing Intrinsic Transistor Capacitance

• Intrinsic PN junction capacitance of the driving
  circuit must be added to the load capacitance
  Cload
• Consider the inverter example at left
• Area and perimeter of the PMOS and NMOS
  transistors are calculated from the layout and
  inserted into the circuit model
• NMOS drain area Wn x Ddrain
• PMOS drain area Wp x Ddrain
• NMOS drain perimeter 2 (Wn Ddrain)
• PMOS drain perimeter 2 (Wp Ddrain)
• SPICE simulations were done (bottom left) for a
  fixed extrinsic load of 100fF with increasing
  transistor width (Wp/Wn 2.75)
• Results show diminishing returns beyond a certain
  Wn (say about 6 um) due to effect of the
  increasing drain capacitance on the overall
  capacitive load

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Area x Delay Figure of Merit

• Increasing device width shows diminishing returns
  on propagation delay time
• Define a figure of merit as area x delay for the
  inverter circuit
• Increasing device width Wn shows a minimum in
  area x delay product
• Unconstrained increase in transistor width in
  order to improve circuit delay is often a poor
  tradeoff due to the high cost of silicon real
  estate on the wafer!!

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Power dissipation
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Why worry about power?-- Heat Dissipation
microprocessor power dissipation
DEC 21164
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Why worry about power Portability
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Where Does Power Go in CMOS?

• STATIC POWER---NIL

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Power consumption

• 4 components
• Static power consumption
• Short circuit power consumption
• Leakage power consumption
• Dynamic power consumption

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Static power consumption
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Short circuit power
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CMOS Short-Circuit Power Dissipation Derivation
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Short Circuit Path
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• The total power in a CMOS circuit is given by
  Ptotal Pd Psc Ps where
• Pd is the dynamic average power (previous chart),
  
• Psc is the short circuit power,
• and Ps is the static power due to ratio circuit
  current, junction leakage, and sub-threshold Ioff
  leakage current
• Short circuit current flows during the brief
  transient when the pull down and pull up devices
  both conduct at the same time where one (or both)
  of the devices are in saturation

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• For a balanced CMOS inverter with ?n?p, and Vtn
  Vtp, the short circuit power can be expressed
  by
• Psc (?/12)(Vdd 2Vt)3 (tr/f/tpin)
  
• where tpin is the period of the input waveform
  and trf is the total risetime (or falltime) tr
  tf trf

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Modelling
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t1- t2, Mos operates in saturation At t2,
current reaches its maximum value At this point
vinvdd/2, because inverter is symmetrical I
mean 2x 2/T x ?Isat dt Limits(t1,
t2) ConditionsVin(t)(Vdd/t) t --assume vin
increases linearly with time tr tf trf Psc
(?/12)(Vdd 2Vt)3 (trf/tpin)
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Effect of load cap on short circuit power

• P short circuit reduces
• Reason---- output start switching after input has
  completely stabilized

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Effect of Cload
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Dynamic power consumption
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Average Dynamic Power in CMOS Inverter

• Average dynamic power derivation
• On negative going input, pull-up device charges
  the load capacitance. On positive going input,
  pull-down device discharges the load into ground.
  
• Average power given by
• Pave (1/T)?CL (dvout/dt) (Vdd vout)dt
  (1/T)?(-1) CL (dvout/dt) vout dt where the
  first integral is taken from 0 to T/2 and the
  second integral is from T/2 to T
• completion of the integral yields
• Pave CL Vdd2 f where f 1/T
• Note that the dynamic power is independent of the
  typical device parameters, but is simply a
  function of power supply, load capacitance and
  frequency of the switching!

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Dynamic Power Consumption - Revisited
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Power Consumption is Data Dependentuniform
distribution of inputs
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Transition Probabilities for Basic Gates
Non-uniform distribution of inputs
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No feedback
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Power consumptionCorrelated signals
½
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Leakage power consumption
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Power delay product
Indicates that energy required ? 0 for Vdd? 0
? erroneous
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Energy delay product
Shd. Be minimum
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Energy delay productoptimum Vdd
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Combinational logicSTATIC CMOS
GATESasynchronous designCan Be Made
Synchronous By Inserting Latches in between
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Design Styles Full Static CMOS or complementary
logic
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NOR
NAND
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XOR/ XNOR
DRAWBACK complementary signals are required
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F D A. (BC)
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Delay computation NAND worst case
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static CMOS gateVTC--Input data dependent
(R1R2) (CL) R1C1)
(R1R2) CL
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Uniform transistor sizing

• For the gate, Find equivalent inverter model
• Find the required transistor w/L
• Hence estimate w/L of each transistor

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Influence of fan-in / fanout on propagation delay
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Other delay reduction techniques

• Progressive transistor sizing
• Input reordering
• Logic restructuring

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Reduce power consumption

• Reduce switching activity

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Power consumption due to glitches
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Logic restructuring for glitch reduction
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Logic restructuring
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Input reordering affects
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Time multiplexing of resources
Very low switching activity
Very high switching activity as bus toggles
between 0 and 1
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Other design styles--Pseudo NMOS
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DCVSL
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Xor/ Xnor
ADVANTAGE---TRANSISTOR SHARING
DCVSL is advantageous for full adder
implementation Then static CMOS
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NAND/ AND
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Logical effortSIMPLE MODEL FOR DELAY ESTIMATION
FOR STATIC GATE LOGIC

• FULL STATIC CMOS

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CKT DESIGN PROBLEMS

• Chip designers face a bewildering array of
  choices.
• What is the best circuit topology for a function?
• How large size should the transistors be?
• How many stages of logic give least delay?

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Need of simple delay model

• Circuit designers waste too much time simulating
  and tweaking circuits
• High speed logic designers need to know where
  time is going in their logic
• CAD engineers need to understand circuits to
  build better tools

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Delay in a Logic Gate
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Delay contributors

• ? is speed of basic transistor
• p-intrinsic delay of the gate due to its own
  internal parasitic capacitances
• H?combines the effect of external load with sizes
  of transistors
• G? effects of circuit topology, fan-in

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Estimation of ?
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CMOS Ring Oscillator Circuit

• An odd number of inverter circuits connected
  serially with output brought back to input will
  be astable and can be used an an oscillator
  (called a ring oscillator)
• Ring oscillators are typically used to
  characterize a new technology as to its intrinsic
  device performance
• Frequency and stage are related as follows
• f 1/T 1/(2n?P)
• where n is the number of stages and
• ?P is the stage delay

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Observations

• Logical effort describes relative ability of gate
  topology to deliver current (defined to be 1 for
  an inverter)
• More complex gates have greater logical effort
  and parasitic delay
• Electrical effort is the ratio of output to input
  capacitance
• Delay increases with electrical effort

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Computing Logical Effort
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Different gates
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Observations

• More complex gates have larger logical efforts.
• Complex gates exhibit high g, greater delay
• Logical efforts grow with increase in no. of
  inputs

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Parasitic delay

• It is fixed for a gate
• More complex gatehigher parasitic delay
• Pinv1 (inverter parasitic delay )
• For other gates , parasitic delay is written in
  terms of pinv

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Parasitic delay
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How to compute Pinv

• For inv. g1, dabst(hpinv)
• In a given tech. plot dabs vs. h
• Plot would be st. line with slope t,
  intercept-pinv t
• Pinv can be estimated after obtaining t
• Draw similar plot for other gates
• Once t is obtained, g and p of other gates can be
  found out.

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Delay equation plot
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Calculating delay of a gate
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Using LE in design
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Sizing a path for minimum delay
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Branching effort along a path
? Used for sizing for delay
Where BH is
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Observations regarding F

• F depends on only topology and loading
• F is Indep. of transistor sizes
• F is unchanged if inverters are added or removed

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Path Delay D

• Sum of delay of all stages

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Condition for min. path delay
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On Differentiation
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Thus, minimum stage effort of each stage reqd.
for min. delay along a path is
We shd. choose transistor sizes such that stage
effort is same for all blocks
Thus, minimum delay achievable along a path is
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Example
Compute for each stage
i
Apply capacitance transformation backwards
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Transistor sizes
All stages shd. have same sizes C n W LMIN
Cox n is a non zero no. Each stage load 3 (w
l) Cox Lmin size
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Transistor sizes

• Inverter load at the input Cz (1pmos1nmos)
  gate load
• Wnmos Wpmos Lmin Cox
• Here
• CzCL Wnmos Wpmos Lmin Cox 2 Wnmos Lmin
  Cox
• In a given tech., Lmin is fixed, say 1um
• given 1Cg Wmin Lmin Cox
• Then if CZ 100Cg then Wnmos 100 Cg /2 Lmin
  Cox
• Wnmos ½100 Wmin

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Ca Cb Wnmos Wpmos Lmin Cox
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Optimizing no of stages in a path for min. delay
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To find optimum N
If pinv 0,
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For N stages in chain with inverters Best delay
per stage , d gh pinv
d ? pinv
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Graphical sol
As pinv grows, adding inverters become less
advantageous
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Mis-sizing the gate
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Mis number the gates
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Driving Large Capacitances-use LE
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Using Cascaded Buffers
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design

• Determine N, u
• cLun1 cg
• (n1)ln (cL/cg) / ln(u)
• Delayto (cdu cg) / (cdcg)
• Delay total (n1) to (cdu cg) / (cdcg)
• Delay total ln (cL/cg) / ln(u)
• to (cdu
  cg) / (cdcg)
• u(ln u-1) (cd/cg) 0
• U e

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Other logic design styles

• Switch logic