Danie Alex, Bianca Almeida, Kendal Broom, Khurram Iqbal, Michael Smith

1
Phase-Locked Loop Circuit Design II
Danie Alex, Bianca Almeida, Kendal Broom, Khurram
Iqbal, Michael Smith
dpa051000_at_utdallas.edu, bba052000_at_utdallas.edu,
keb053000_at_utdallas.edu, kxi041000_at_utdallas.edu,
mcs055000_at_utdallas.edu
Department of Electrical Engineering Erik Jonsson
School of Engineering Computer
Science University of Texas at Dallas Richardson,
Texas 75083-0688, U.S.A.
Project Results
Project Goals

• Components were wired together successfully with
  the circuit
• software. Multisim was used mostly for real
  time continuous
• analysis. PSpice provided easily manipulated
  graphing capabilities
• 
  
• 
  Graph shows correct operation of
• 
  phase detector. Top two waves are
• 
  inputs of different frequencies.
• 
  bottom wave represents error signal
• 
  sent to the loop filter and then to VCO
• to correct the output frequency.
• 
  Graphs show desired response of
• 
  loop filter.

• To design a phase-locked loop (PLL) which can
  be used for modulation and demodulation of a
  frequency modulated signal, signal regeneration
  and clock recovery.
• The PLL should compare two signals the crystal
  oscillator frequency of the PLL divided by a
  constant, n, and the output frequency of the VCO.
  The output frequency should match the PLL
  crystal oscillator frequency within the lock
  time. For simulation, the crystal oscillator was
  replaced by a voltage source with a set frequency.

Project Overview

• The design of the PLL has four basic components
  The frequency divider, phase detector, loop
  filter, and voltage controlled oscillator (VCO).
  A basic block diagram follows to illustrate the
  basic signal flow of the circuit.
• Actual circuit design built around digital and
  analog circuit components such as junction
  transistors, capacitors and flip flops
• Modes of synthesis will be Multisim and PSpice
  circuit design
• packages
• Project began with extensive research into PLL
  uses
• and operation
• Next, component architecture chosen for each
  block
• 
  The Gilbert Multiplier model (left) was
• 
  chosen as the phase detector

Project Conclusions/Outcomes

• PLL was able to achieve lock for frequency range
  from 30MHz to
• 110 MHz
• Set up time for VCO was about 1.01us
• PLL will only be in lock for a short amount of
  time
• this is referred to as the hold time. After
  the hold time has expired,
• the PLL tends to leave lock to approach the
  free running frequency of the
• VCO. The phenomenon will continue
  indefinitely.
• Our hold time turned out to be about 2us.
• VCO is most important part of circuit. It
  provides output as well as
• Second signal to be compared to input.