DAC Presentation kit - PowerPoint PPT Presentation

1 / 32
About This Presentation
Title:

DAC Presentation kit

Description:

Ping-Hung Yuh1, Chia-Lin Yang1, and Yao-Wen Chang2 ... Avg. 12. 8x7x68. 104. 9x9x130. 8x8x120. 6. 9x8x66. 64. 9x11x99. 10x10x100. 1.0. 1.0. 7.88. 2.42 ... – PowerPoint PPT presentation

Number of Views:20
Avg rating:3.0/5.0
Slides: 33
Provided by: carl290
Category:
Tags: dac | avg | com | kit | presentation

less

Transcript and Presenter's Notes

Title: DAC Presentation kit


1
(No Transcript)
2
Placement of Digital Microfluidic Biochips Using
the T-tree Formulation
  • Ping-Hung Yuh1, Chia-Lin Yang1, and Yao-Wen Chang2

1 Dept. of Computer Science Information
Engineering 2 Graduate Institute of Electronics
Engineering and Dept. of Electrical
Engineering National Taiwan University, Taiwan
3
Outline
  • Introduction
  • T-tree Based Placement Formulation
  • Floorplanning Algorithm
  • Experimental Result
  • Conclusion

4
Outline
  • Introduction
  • T-tree Based Placement Formulation
  • Floorplanning Algorithm
  • Experimental Result
  • Conclusion

5
Digital Microfluidic Biochips
  • Perform laboratory procedures based on liquid
    particles (droplets)
  • The two main components
  • Reconfigurable devices (electrodes)
  • Droplets can move freely on the reconfigurable
    device
  • Non-reconfigurable devices (detectors and
    reservoirs)
  • Only one functionality

Optical detector
Droplets
Storage
Electrodes
The schematic view of a biochip (Duke Univ.)
Mixing two droplets
Reservoirs/Dispensing ports
6
Digital Microfluidic Biochips (contd)
Mix
Storage
Dilution
Time 14
Time 45
Mix
Mix
Dilution
Dilution
a
b
Mix
c
Task graph
Time 57
7
Placement Problem of Biochips
  • Inputs
  • Sequencing graph
  • Microfluidic module library
  • Design specification
  • Fixed architecture (ex 5x5-array) and maximum
    assay completion time (ex 400 sec)
  • Limited number of non-reconfigurable devices
  • Output the schedule and placement of tasks

Microfluidic Module Library
A sequencing graph
8
Previous Work
  • Architecture-level synthesis (scheduling and
    binding)
  • Deng et al, TCAD01
  • Architecture-level model and ILP-based method
  • Su and Chakrabarty, ICCAD04
  • Sequencing graph model and two heuristics
  • Physical placement
  • Su and Chakrabarty, DATE05
  • Simulated annealing based algorithm with given
    scheduled tasks
  • Unified synthesis and placement
  • Su and Chakrabarty, DAC05
  • Parallel recombinative simulated annealing
  • List scheduling and greedy placement method

9
Our Contribution
  • Formulate the execution of a bioassay as a 3D
    floorplan
  • Apply a tree-based representation (T-tree) to
    solve the floorplanning/placement problem

Mix
Storage
Mix
Dilute
Storage
Mix
Time t2
Mix
Mix
Dilute
Mix
Time t1
Time t3
10
Outline
  • Introduction
  • T-tree Based Placement Formulation
  • Floorplanning Algorithm
  • Experimental Result
  • Conclusion

11
Bioassay Execution to 3D floorplan
  • Model each task and storage as a 3D box
  • Model the execution of a bioassay as a 3D
    floorplan
  • Biochip placement problem to 3D temporal
    floorplanning problem

Dilute
Storage
Mix
Time t2
Storage
Mix
Mix
Mix
Mix
Dilute
Mix
Time t1
Time t3
12
Review of T-tree
  • A 3-ary tree representation for
    temporalfloorplanning/placement problem

Mix b
Dilute c
Storagess
Storagess
Mix a
Mix a
Mix b
Dilute c
A 3D compacted floorlpan
The corresponding T-tree
13
Review of T-tree (contd)
  • The T-tree keeps the geometric relation as
    follows
  • Left child adjacent in the T direction
  • Middle child in the Y direction with the same
    t-coordinate
  • Right child in the X direction with the same t-
    and y-coordinates

Mix b
Dilute c
Ti duration of i
Storage s
Storages
Mix a
Mix a
Mix b
Dilute c
ti starting time of i
14
Modeling Tasks in a T-tree
  • Model each task as a node in a T-tree

f
Dispense
c
e
a
b
d
The corresponding T-tree
A sequencing graph
15
Modeling Storages
  • Model each storage as a node in a T-tree
  • Each edge in a sequencing graph represents a
    storage

f
Dispense
c
e
s2
s1
Storage
a
b
s2
s1
s4
s3
d
s5
s3
s4
s5
The corresponding T-tree
A sequencing graph
16
Modeling Storages (contd)
  • The storage constraint the duration of one
    storage covers the time gap between two
    data-dependent tasks
  • Insert a storage node in one of the feasible
    locations in a T-tree
  • Ensure that ts tb Tb

t
c
s
Tb
b
feasible location
b
tatbTb
tb
tdteta
a
s
d
c
e
Example of feasible locations
17
Modeling the Design Specification
  • The fixed-cube constraint
  • Model the fixed architecture and max. completion
    time as a 3D cube
  • A feasible floorplan must be within this 3D cube
  • The resource constraint
  • of non-reconfigurable tasks is limited at any
    time
  • Add the virtual edges in the sequencing graph

Virtual edge
Max. completion time
A feasible floorplan
Fixed architecture
18
Outline
  • Introduction
  • T-tree Based Placement Formulation
  • Floorplanning Algorithm
  • Experimental Result
  • Conclusion

19
Floorplanning Algorithm
  • Based on simulated annealing (SA)
  • The modified SA flow
  • Detect the violation of the storage constraints
  • Delete unused storages in a T-tree for packing
    efficiency

Perturbation
Storage Constraint
Feasibility Detection Tree Reconstruction
Data Dependency
Number of storagesAdjustment
Packing
Termination?
No
Yes
20
Floorplanning Algorithm (contd)
  • Cost function
  • Volume
  • of storages
  • Penalty term for fixed-cube constraint

21
Two Methods for Fixed-cube Constraint
  • Guide the tree perturbation based on cube
    violation probability pw, ph, and pt
  • pw k/n, where k is the of floorplans whose
    width exceeds the 3D cube in the last n
    iterations
  • If pw is large, increase the probability of
    placing tasks along the Y or T direction
  • Add the excessive length into the cost function

An infeasible floorplan
Max. completion time
Excessive length
Fixed architecture
22
Outline
  • Introduction
  • T-tree Based Placement Formulation
  • Floorplanning Algorithm
  • Experimental Result
  • Conclusion

23
Experimental Settings
  • Implemented our algorithm in C language on a
    1.2 GHz SUN Blade-2000 machine with 8GB memory
  • Implemented the algorithm of Su and
    Chakrabarty, DAC05 on the same machine
  • Tested two bioassays
  • Colorimetric protein assay from Su and
    Chakrabarty, DAC05
  • Multiplexed in-virto diagnostics from Su and
    Chakrabarty, ICCAD04
  • Assigned three different design specifications
    (fixed-cube constraints) to each bioassay

24
Experimental Result
Bioassay DesignSpec. Su et al, DAC05 Su et al, DAC05 T-tree T-tree
Bioassay DesignSpec. Volume CPU time(seconds) Volume CPU time(seconds)
ProteinSu et al, DAC05 10x10x400 9x10x400 300 10x10x270 89
ProteinSu et al, DAC05 10x10x360 10x10x342 225 10x10x282 119
ProteinSu et al, DAC05 11x11x320 8x13x269 208 11x11x238 66
Avg. 1.16 2.67 1.0 1.0
In vitro Su et al, ICCAD04 10x10x100 9x11x99 64 9x8x66 6
In vitro Su et al, ICCAD04 8x8x120 9x9x130 104 8x7x68 12
In vitro Su et al, ICCAD04 7x7x140 9x10x105 92 6x7x89 15
Avg. 2.42 7.88 1.0 1.0
volume area assay completion time
Result that cannot satisfy the fixed-cube
constraint
T-tree based algorithm is more efficient and
effective
25
Resulting Placement of the Protein Bioassay
Volume 10x10x270 (10x10x400 fixed-cube
constraint)
26
Outline
  • Introduction
  • T-tree Based Placement Formulation
  • Floorplanning Algorithm
  • Experimental Result
  • Conclusion

27
Conclusion
  • Formulated the placement problem of biochips as
    the temporal floorplanning problem
  • First work to apply a topological representation
    to the placement problem of biochips
  • Demonstrated the effectiveness and efficiency of
    our algorithm
  • Future work
  • Consider fault and defect tolerance during
    floorplanning

28
Thank you for your attention
29
Q A
r91089_at_csie.ntu.edu.tw
30
Question 1
  • Q Why choose the T-tree representation over
    other 3D representations (3D-subTCG, ST,
    3D-slicing tree) ?
  • A Three reasons
  • 1. T-tree models the compacted floorplan, thus it
    has the advantage of volume optimization
  • 2. T-tree is more efficient for large-scale
    circuits than 3D-subTCG, ST
  • 3. T-tree is more effective in handling the
    storages
  • T-tree can determine the of storages and
    duration of each storage before packing with only
    O(n) time
  • 3D-subTCG and ST needs O(n2) time before packing
  • 3D-slicing tree cannot obtain this information
    before packing
  • It is difficult for 3D-slicing tree to satisfy
    the storage constraint

31
Question 2
  • Q Why add the of storages in the cost
    function?
  • A Two reasons
  • 1. Generally, the smaller of storages, the more
    compact 3D floorplan we can have
  • 2. Release the volume occupied by storages for
    reconfigurable task to use

32
Question 3
  • Q Why your algorithm is better than previous
    work?
  • A There are two reasons
  • 1. T-tree is better in volume optimization than
    previous greedy placement method
  • 2. Smoother optimization process by minimizing
    volume instead of area plus completion time
Write a Comment
User Comments (0)
About PowerShow.com