Combinational Logic II

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Combinational Logic II

• Instructor Koling Chang
• email kchang_at_cs.ucdavis.edu

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Outline

• Comparator
• XOR
• Adder
• Fixed-point Arithmetic
• ALU

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Comparators

• Compare two sets of input signals (A,B) and
  generate 1 or 0 (True or False) on the following
  signal lines
• AB
• AgtB
• AltB

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Comparator

• Logic for AB using XOR gates

All 0s if AB
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Using XOR

• A XOR B AB AB
• If A!B, AB
• A XOR B AAAA A A 1
• Using XOR as Controlled Inverter
• If A 1 then AXORB B, else A XOR B B
• Used as the sum of an adder

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gt And lt
A3
B3
A2
A3 B3
B2
gt
A3-2 B3-2
A1
B3
A0
A3-1 B3-1
B0
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Comparator (cont.)

• 4-bit magnitude comparator chip

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Larger Size Comparator

• Using multiple small comparators to build a large
  one using expansion inputs
• If A1 ! B1, then A!B
• If A1 B1, A2B2, then AB
• How about gt and lt?

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Comparator (cont.)

• Serial construction of an 8-bit comparator

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Adders

• 1
• 1
• 10

A
B
C
O
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Adders

• Half-adder
• Adds two bits
• Produces a sum and carry
• Problem Cannot use it to build larger inputs
• Full-adder
• Adds three 1-bit values
• Like half-adder, produces a sum and carry
• Allows building N-bit adders
• Simple technique
• Connect Cout of one adder to Cin of the next
• These are called ripple-carry adders

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Adders (cont.)

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Adders (cont.)

• A 16-bit ripple-carry adder

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Adders (cont.)

• Ripple-carry adders can be slow
• Delay proportional to number of bits
• Carry lookahead adders
• Eliminate the delay of ripple-carry adders
• Carry-ins are generated independently
• C0 A0 B0
• C1 C0(A1B1)A1B1 A0 B0 A1 A0 B0 B1 A1 B1
• C2 C1(A2B2)A2B2 A2A0B0A1A2A0B0B1A2A1B1
  B2A0B0A1 B2A0B0B1 B2A1B1A2B2
• Requires complex circuits
• Usually, a combination carry lookahead and
  ripple-carry techniques are used

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Carry Lookahead

• All logic function can be in the form of SOP.
• Only two-level of gate delay
• generate gi xiyi
• propagate pi xiyi
• carry ci gipici-1

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Carry Lookahead (cont.)
A
B
Ai
Bi
A
B
O
Oi
O
C
Ci
C
g
p
Carry-lookahead circuit
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Adders (cont.)

• 4-bit carry lookahead adder

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Fixed-Point Arithmetic

• Number Representation
• Unsigned
• Signed
• Sign and magnitude
• 1s complement
• 2s complement
• Excess-M Representation ( does not have same
  positive number representations )

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Number Representation
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2s Complement

• Same positive number presentation
• Leading sign bit
• Defined as N 2n N N 1
• Addition logic Subtraction logic
• Easy overflow detection
• Widely used by all processors

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2s Complement Example

• 5 0101 B
• -5 24 5 16-5 11 1011B

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Overflow Detection

• Unsigned Numbers
• If there is a carry-out from the MSB
• Signed Numbers
• Adding two positive numbers results a negative
  number
• Adding two negative numbers yields a positive
  number.

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1s Complement

• Similar logic operations with 2s complement with
  end-around carry
• 0101 0011 0101 1100
• 1 0001
• 0010
• Frequently used in checksum calculation
• byte order independent
• cumulative and associative
• deferred carries
• incremental update

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Arithmetic and Logic Unit

• Preliminary ALU design

Cin F1F0 or just F0
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Arithmetic and Logic Unit (cont.)

• Final design

Cin F0
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Arithmetic and Logic Unit (cont.)

• 16-bit ALU

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Arithmetic and Logic Unit (cont.)

4-bit ALU