Arithmetic and CAD Tools

1
Arithmetic and CAD Tools

• CAD tools work great with arithmetic functions
• Adding,subtracting,multiplying, etc.
• A few things to learn first
• How to work with multi-bit numbers in CAD tools
  and VHDL
• How to create custom components in CAD tools
• I.e. a 7-bit adder/subtractor
• How to include VHDL components in a larger
  schematic

2
Multi-bit Numbers - Busses

• In Quartus II Schematics
• Busses are collections of wires
• mybus7..0 is an eight bit bus
• Composed of mybus7 (MSB) through mybus0 (LSB)
• Busses make it easier to draw circuit diagrams
• In VHDL
• Busses are defined as a type of STD_LOGIC
• X STD_LOGIC_VECTOR (7 DOWNTO 0)
• Composed of X(7) through X(0)

3
Connecting by name in Schematics

• Nodes (wires) can be connected by name
• Reduces complexity of drawing

• Input names
• Can be used on any wires
• All wires of the same name are connected

• Intermediate node names
• Just name it no need to define it

• Busses
• Can connect a single wire from a bus by name

4
Busses in Schematics

• Many components have bus inputs
• Adders, for example

• Busses use thick lines
• Drawing from a bus input automatically makes a
  bus
• May select thick line from the line style menu

• Connecting busses
• Just name them the same thing

• Making busses out of wires
• Type all of the components (MSB to LSB) separated
  by commas

5
Creating and Using Custom Schematic Symbols
1. Make your component. Inputs/Outputs are
interface to higher level
2. File Create/Update Create Symbol File For
Current File
3. Make a new schematic for your main file and
use your new symbol!
6
Making and Using Custom VHDL Symbols
1. Make your component. Inputs/Outputs are
interface to higher level
2. File Create/Update Create Symbol File For
Current File
3. Make a new schematic for your main file and
use your new symbol!
7
MegaFunctions

• Quartus II has many configurable megafunctions
• Adders, subtractors, muxes, etc.

• Use the MegaWizard
• Button on the insert symbol menu

• Answer all of the questions
• see next slide

• Save the new part
• Insert it into your schematic

8
Using the MegaWizard

1. Choose Create a new to make a new device

2a. Pick a megafunction to useArithmetic
includes adders, subtractors, counters,
multipliers, etc.Gates include multiple-bit
variations of standard logic.
2b. Choose VHDL and give your part a name.
9
Using the MegaWizard
3. Pick options Data bus width Modes Etc.
10
Using the MegaWizard
4. Decide if any inputs are constants (i.e.
always adding 4)
11
Using the MegaWizard
5. Pick optional outputs Adder has optional
carryin, carryout, and overflow out.
12
Using the MegaWizard
6. Pipelining advanced option to speed up the
function. Dont use for now.
13
Using the MegaWizard
7. Just click Finish
14
Using the MegaWizard
9. Now your new symbol is available for use in
schematics!
8. Yes add to your project so you can use it!
15
Using Busses in VHDL
Must use the IEEE library to use STD_LOGIC
LIBRARY ieeeUSE ieee.std_logic_1164.all ENTITY
hextosevenseg IS PORT( N IN STD_LOGIC_VECTOR(3
downto 0) a,b,c,d,e,f,g,dec
OUT STD_LOGIC)END hextosevenseg ARCHITECTURE
logicfunc OF hextosevenseg IS BEGIN a lt
NOT( (N(2) AND N(1) AND NOT N(3)) OR
(N(1) AND NOT N(2) AND N(0)) ) b lt
END logicfunc
Bus definition
Using bus signals individually
16
Math in VHDL
Must use the SIGNED library for math
LIBRARY ieeeUSE ieee.std_logic_1164.allUSE
ieee.std_logic_signed.all ENTITY addemup
IS PORT( A,B IN STD_LOGIC_VECTOR(15 downto
0) Sum OUT STD_LOGIC_VECTOR(15 downto
0))END addemup ARCHITECTURE logicfunc OF
addemup IS BEGIN Sum lt A B END logicfunc
Were adding two 16-bit numbers and producing a
16-bit sum
Its this easy!
17
Decisions in VHDL using IF/THEN/ELSE
LIBRARY ieeeUSE ieee.std_logic_1164.allUSE
ieee.std_logic_signed.all ENTITY addemup
IS PORT( A,B IN STD_LOGIC_VECTOR(15 downto
0) Sub IN STD_LOGIC Out
OUT STD_LOGIC_VECTOR(15 downto 0))END
addemup ARCHITECTURE logicfunc OF addemup
IS BEGIN PROCESS(Sub,A,B) BEGIN IF (Sub
0)THEN Out lt A B ELSIF (Sub
1)THEN Out lt A B ELSE Out lt
0000000000000000 END IF END PROCESSEND
logicfunc
Expand adder to adder/subtractorSub1 ?
subtract, Sub0 ? Add
PROCESS Identify which inputs may cause output
to change
Scalar constantsin single quotes
IF / ELSIF / ELSE / END IFDecision-making
statements
Vector constantsin double quotes
Dont forget to END IF and PROCESS
18
Truth Tables in VHDL
LIBRARY ieeeUSE ieee.std_logic_1164.allENTITY
simplefunction IS PORT( A IN STD_LOGIC_VECTOR(1
downto 0) Z,Q OUT STD_LOGIC)END
simplefunctionARCHITECTURE logicfunc OF
simplefunction IS BEGIN PROCESS(A) BEGIN C
ASE A IS WHEN 00 gt zlt0qlt0 WHEN
01 gt zlt1qlt1 WHEN 10 gt
zlt1qlt1 WHEN 11 gt
zlt0qlt1 WHEN OTHERS
gtzlt0qlt0 END CASE END PROCESS END
logicfunc
Process block specifies input(s) to process
Vector constantsin double quotes
Scalar constantsin single quotes
A case for each rowin truth table
Others catches any unlisted cases. Use it even
if you covered them all.