Laboratories and Materials Teaching Hardware-Software Co-Design

1
Laboratories and Materials Teaching
Hardware-Software Co-Design

• D.G. Beetner and H.J. Pottinger
• Electrical and Computer Engineering
• University of Missouri-Rolla

2
Outline

• Background and Motivation
• Overview
• Introductory Example
• Laboratory Exercises
• Detailed Example
• Evaluation

3
Background

• Hardware and software developed separately in
  past
• Increasingly risky
• Systems on a Chip
• Short market windows
• Difficult to partition hardware and software
• Co-Design reduces number of prototypes and
  time-to-market
• Rapidly growing demand

4
Background

• Hardware-Software Co-design fundamental to
  digital systems design
• Undergraduates in CpE, EE, and CS should be
  introduced to this concept
• Developed software and laboratories which
  introduce Co-design at the junior level

5
Laboratory Objective

• Teach concepts of microcontrollers and
  hardware-software co-design
• Hardware-Software partitioning
• Re-use of intellectual property (IP)
• Hardware-Software co-simulation
• Embedded software in C and ASM
• Communication with external devices
• Real-time systems

6
Course Design

• Associated course
• Junior level
• Focused on 8051 microcontroller
• Mix of CpE, EE, and CS students
• Lab is not required
• Student background
• C
• Electronic design automation tools
• Rapid prototyping with FPGAs

7
Experiment Outline

• Develop and simulate software
• Develop and simulate hardware
• Co-simulate hardware and software
• Verify design in hardware

8
Laboratory Equipment

• Keil Software Development Tools
• C and ASM
• 8051 software simulation
• Free evaluation software

9
Laboratory Equipment

• Mentor Graphics design automation tools
• 8051 simulation model
• Clock-cycle accurate
• Executes compiler-generated code
• Complete functionality

10
Laboratory Equipment

• Mentor Graphics design automation tools
• 8051 simulation model
• Clock-cycle accurate
• Executes compiler-generated code
• Complete functionality

11
Laboratory Equipment

• XS40 board by Xess corporation
• 8031 microcontroller
• Xilinx FPGA
• VGA port
• 7-segment LED
• Generous pin-probe points

12
Experiments

• Several labs developed
• Introduction to Hardware-Software Co-Simulation
• Hardware-Software Co-Verification
• Extending the 8051 with External Hardware
• Design with intellectual property Creating a VGA
  display
• Bi-directional serial communication with
  interrupts

13
Projects

• Digital LCD alarm clock
• Virtual pet
• MP3 player controller
• Pong game
• Automatic pet feeder
• Simon game

14
Introductory Example 7SegDisp

• Objectives
• Instructors overview of
• 8051 model usage
• Co-verification methodology
• Extension to exclusive VHDL approach
• Implement
• 8051 address latch
• Seven segment display output port

15
7SegDisp Overview

• Similar to UMR Lab Exercise 4
• A collage of labs 1, 4, and 5
• Construct an eight bit latch for use as
• Address latch for 8051 expanded mode
• Output port for seven segment display on XS40
• Construct an address decoder for output port at
  0x7F55
• Interface to XS40 starting frame model
• Write and test C program to display message
• Simulate entire system and test on XS40 hardware

16
Block Diagram of 7SegDisp
17
7SegDisp Specifications

• Must execute 8051 code from XS40 Sram
• Sram is 32k bytes from 0x0000 to 0x7FFF
• Latch data for seven segment display
• Display port in xdata at address 0x7F55
• Software to display 0123456789 continuously at
  one second intervals

18
Lab Sequence Overview

1. Eight bit latch design
2. Intro to H/W S/W Co-simulation
3. Hardware verification of Gnome S/W
4. Extending the 8051
5. Single chip memory spaces for 8051
6. Design with IP a VGA controller
7. Bidirectional Serial I/O using interrupts

19
Ex 1 Eight Bit Latch Design

• 8-bit parallel port using an FPGA
• Re-familiarize with Design Architect
• Simulate hardware with Quicksim
• Familiarization with XS40 board
• Use a PC to provide stimulus to hardware
• Compare hardware and simulation model response

20
Ex 2 Intro to Co-simulation

• Write assembly program to multiply two 4-bit
  numbers
• Hand assemble and create Intel hex file
• Verify using a hardware model
• Illustrate importance of simulation
• Currently using Xess GNOME processor

21
Ex 3 Hardware Verification

• Familiarization with XS40 Board
• Tradeoffs between simulation and hardware testing
• Use of oscilloscope and logic analyzer
• Fix unexpected change in hardware
• Infer internal behavior by observing external
  signals

22
Ex 4 Extending the 8051

• Add address latch and external output port
• Improve hardware-software design skills
• Demultiplex 8051 address/data bus
• Observe timing of 8051 bus signals
• Introduce 8051 simulation model
• More familiarization with XS40 board

23
Ex 5 Single Chip Memory Spaces

• Implement xdata and code space in SRAM
• Xdata at 0x5000
• Code at 0x0000
• Write message display program in assembly
  language
• Use of software development tools
• Illustrate importance of hardware/software
  co-verification
• Students write software and make small
  modification to previous hardware design

24
Ex 6 Design with IP

• Develop interface to a VGA controller soft macro
• VGA core implements 16 x 8 character display
• Write message display program in C for 8051
• Reinforces importance of co-verification
• VGA core is a non-standard 8051 peripheral
• Need to verify both HW and SW operating together

25
Ex 7 Serial Communication

• Bi-directional comm with two serial ports
• Design system that can communicate with another
  groups XS40 board
• Use interrupts to service serial port
• Design re-use (modification of lab 6)
• Re-inforce co-verification techniques
• Improve C programming skills

26
HW-SW Co-design Process
Hardware Verification
27
HW-SW Co-design Process
Hardware Verification
28
HW-SW Co-design Process
Hardware Verification
29
HW-SW Co-design Process
Hardware Verification

• QuicksimPro
• Quicksim
• Modeltech

30
HW-SW Co-design Process
Hardware Verification
Xilinx Alliance
31
Hello World Program
Specification Display each char of message for
two seconds With a one second pause in
between Seven segment display port at 0x7f55 Bit
0 is segment a, bit 6 is segment g
define SEG7 XBYTE0x7F55 void main () static
code char msgtxt "0123456789" char code
cptr TMOD0x01 / 16bit timer mode / while
(1) cptr msgtxt while(cptr) SEG7
decode(cptr) // pause between
characters ifndef SIMULATION delay(2) SEG7
0 delay(1) endif / while (cptr) /
/ while(1) /
Get next char
Lookup segment values
Pause if not simulating
no
Done?
32
Keil ?vision IDE
33
Keil ?vision Debugger
34
Lab 4 Starting Frame

• Archive file with simulation model etc.
• XS40 schematic model
• 8051 model
• 32k sram model
• Clock, seven segment display, etc models
• XC4005 FPGA starting frame
• Hello world hex object file hello.hex
• Results of previous lab eight bit latch

35
XS40 Schematic model
36
8051 Model

• 8051 Schematic symbol is linked to an underlying
  VHDL behavioral model

37
Sram model (1)
Sram wrapper
Address map
Sram symbol
38
Sram model (2)

• SRAM model is a modified version of Andre
  Klindworths VHDL model

39
XC4005 Starting Frame
40
Address latch sample solutions
Typical student solution
The answer book!
41
Sample solution for mydecoder
42
Finished FPGA schematic model

• Screen shot of finished xc4005

43
Closeup of finished schematic
44
Linking program file to model

• Closeup of file property, hello.hex, and dir
  listing

45
QSPro Simulator

• Mixed Schematic and VHDL models
• Gate level plus VHDL simulator
• QSPro startup ?

46
QSPro Simulation Environment

• Screenshot of A typical simulation setup

47
8051 Startup Timing
48
7SegDisp Write Cycle

• Screen shot of cycle showing a write to 7f55

49
Lab Equipment

• A picture of a typical lab setup

50
Comparison of Hardware and Simulation Results
Simulation trace
Scope trace
51
A VHDL-basedHW-SW Co-design Process
software
hardware
Hardware Verification
52
Evaluation

• Technical accuracy of models
• Educational effectiveness of labs

53
Evaluation of Models

• Standard software-testing methodologies
• White-box testing
• ASM and VHDL testbenches
• Code coverage (line coverage, decision coverage,
  etc)
• Evaluation in lab by students and instructors
• Bugs found and eliminated

54
Evaluation of Labs

• Compared students who took the lab VS those who
  did not
• Students who took the lab
• Performed 33 better on evaluation exam
• Received 20-30 higher final grade in lecture
  course
• About 1 letter grades higher on tests
• Little difference between students in other CpE
  courses

55
Acknowledgements

• National Science Foundation Course Curriculum and
  Laboratory Improvement program, DUE-9952540
• Mentor Graphics
• Keil Software
• Jim Frenzel, University of Idaho
• Dave Van Den Bout, XESS Corp.
• Xilinx

56
Mentor Graphics Higher Education Program (HEP)

• Includes all of Mentor Graphics EDA tools
• 2100 per year for 10 seats
• Free training classes
• Very active university support group
• Contact shanthi_pattison_at_mentorg.comor post to
  univ_sig_at_mentorug.org

57
Xilinx University Program (XUP)

• Contact
• anna.acevedo_at_xilinx.comor
  http//www.xilinx.com/univ/

58
Questions/Comments ?

• Submit questions/comments
• Using chat screen
• Via email
• daryl_at_umr.edu
• hjp_at_umr.edu