Karnaugh Map

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Karnaugh Map and Circuit Design
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• Four Variable MAP
• The map minimization for fourvariable Boolean
  functions is similar to the method used to
  minimize three variable functions.
• Adjacent squares are defined to be square next to
  each other.
• In addition, the map is considered to lie on a
  surface with the top and bottom edges, as well as
  the right and left edges touching each other to
  create adjacent squares.
• For example, m0 is adjacent to m2, and m4 is
  adjacent to m6 because the minterms differ by
  one variable.

y
yz wx
01
10
11
00
00
01
x
11
w
10
z
3

• This can be proved by
• m0 m2 wxyz wxyz wxz(yy)
  wxz
• m4 m6 wxyz wxyz wxz (yy) wxz
• One squares represent one minterm given a term of
  four literals
• Two adjacent squares represents a term of three
  literals
• Four adjacent squares represents a term of two
  literal
• Eight adjacent squares make one literal
• Sixteen adjacent squares represent the function
  equal to 1.

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• Example Simply the Boolean function
• F (w,x,y,z) S (0,1,2,4,5,6,8,9,12,13,14)
• Since the function has four variables, a four
  variable map must be used.
• The minterms listed in the sum are marked by 1s
  in the map.
• 8 adjacent squares marked with 1s can be
  combined to form the single literal term y.
• The remaining three 1s on the right cannot be
  combined to give a simplified term
• They must be combined as two or four adjacent
  squares

y
yz wx
10
11
00
01
00
01
x
11
w
10
z
5

• The top two 1s on the right are combined with
  the top two 1s on the left to give the term wz
• Note that it is permissible to use the same
  square more than once
• Now we are left with the squares marked by 1 in
  the third row (m14)
• Instead of taking this square alone (which will
  give a term of 4 literals), we combine it with
  squares we have used in order to form an area of
  4 adjacent squares
• These 4 adjacent squares made up the two middle
  rows and the two end columns giving the term xz
• The simplified function is
• F y wz xz

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• 5 variable map
• Maps for more than four variables are not simple
  to use. A five variable map needs 32 squares and
  a 6 variable map needs 64 squares
• When the number of variables becomes large, the
  number of squares becomes excessively large and
  the geometry for combining adjacent squares
  become involved
• Consider the following 5 variable map

A 0
A 1
D
D
DE BC
DE BC
00
01
10
11
00
01
10
11
00
00
01
01
C
C
11
11
B
B
10
10
E
E
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• The five variable map consists of two four
  variables map with variables A, B, C, D and E
• Variable A distinguishes between the two maps as
  indicated on the top of the diagram
• The left hand side four variable map represents
  the 16 squares (minterms 0-15) where A0 and the
  other four variable map represents the squares
  (minterms 16-31) where A1
• Each four variable map retains the previously
  defined adjacency when taken separately
• In addition, each square in the A0 map is
  adjacent to the corresponding square in the A1
  map
• For example, m4 is adjacent to m20 and m15 is
  adjacent to m31

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• Example Simplify the Boolean function
• F (A, B, C, D, E) (0, 2, 4, 6, 9, 13, 21, 23,
  25, 29, 31)
• Four adjacent squares in the A0 map are combined
  to give the three literal term ABE
• The two squares in column 01 and the last two
  rows are combined to both parts of the map to
  give three literal term BDE
• The term ACE is obtained from the four adjacent
  square that are entirely within the A1 map

A 0
A 1
D
D
DE BC
DE BC
00
01
10
11
00
01
10
11
00
00
01
01
C
C
11
11
B
B
10
10
E
E
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• NAND and NOR implementation
• Digital circuits are frequently constructed with
  NAND or NOR gates rather than AND or OR gates
• Because of the importance of NAND and NOR gates
  in the design of digital circuits, rules and
  procedures have been developed for the conversion
  from Boolean function in terms of AND, OR and NOT
  into equivalent NAND and NOR logic diagrams

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• NAND Circuits
• The NAND gates is set to be the universal gate
  because any digital system can be implemented
  with it
• To show that any Boolean function can be
  implemented with NAND gates we need to show that
  the logical operations of AND, OR and COMPLEMENT
  can be obtained with NAND gates only as follows

x
x
Implementing Complement with NAND
(xy)
Implementing AND with NAND
AND
xy
x
x
Implementing OR with NAND
(xy) x y
OR
y
y
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• To implement a Boolean function with NAND gates,
  the function should be in sum of product form.
• To see the relationship between the sum of
  product expression and its equivalent NAND
  implementation, consider this function.
• F ABCD
• These three circuits are equivalent and implement
  the function F.

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• The function is implemented with AND and OR
  gates. The AND gates are replaced by NAND gates
  and the OR gate is replaced by NAND gate.
  OR-invert graphic symbol on the second circuit is
  another symbol for NAND gate.
• Remember that a bubbles denotes complementation
  and two bubble along the same line represent
  double complementation, so both can be removed.
• Removing the bubbles on the second circuit
  produces the first one, so both diagrams are the
  same.
• The NAND representation on the third circuit can
  be verified algebraically (by DeMorgan law) that
  represents the same function.
• F ((AB)(CD)) AB CD

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• Example
• Implement the following Boolean function with
  NAND gates
• F(x,y,z) (1,2,3,4,5,7)
• The first step is to simplify the function in sum
  of product, using three variable map
• F xy xy z

y
yz x
10
00
11
01
0
1
x
z
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• Draw NAND gate for each product term of the
  expression that has at least two literals. These
  constitute the first level gates.
• Draw single gate using the NAND gate or
  OR-invert for second level, with input coming
  from the output of first level gates.
• A term with a single literal requires an inverter
  in the first level. However, if the single
  literal is complemented, it can be connected
  directly to the input of second level NAND gate

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• Different digital circuits
• Logic circuits for digital systems may be
  combinational or sequential
• A combinational circuit consists of logic gates
  whose outputs at any time are determined from the
  present combination of inputs.
• Sequential circuits will be defined later in the
  course.

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• Design Procedure of Combinational Circuit
• The design of a combinational circuit starts from
  the specification of the problem, which can be
  implemented in a logic circuit diagram or a set
  of Boolean function .
• The procedure involves the following steps
• From the specifications of the circuit, determine
  the required number of inputs and outputs and
  assign a symbol to each
• Derive the truth table that defines the required
  relationship between inputs and outputs.
• Obtain the simplified Boolean function for each
  output as a function of the input variables
• Draw the logic diagram and verify the correctness
  of the design.

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• Design of Binary Adder
• The most basic arithmetic operation is the
  addition of two binary digits
• This simple addition consists of four possible
  elementary operations
• 000, 011, 10 1 and 111 0
• The first three operations produce a one digit
  number as a result, but when both augends and
  addend bits are equal to 1, the binary sum
  consist of two digits (10).
• The higher significant bit of this result is
  called a carry
• The lower significant digit is sum
• The combinational circuit that performs the
  addition of two bits is called half adder

Carry
Sum
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• Half Adder
• Half adder circuits needs two binary inputs and
  produce two binary outputs.
• The input variables are the augends and addend
  bits the output variables are sum (s) and carry
  (c)
• In this circuit x and y are input and S and C are
  the output
• The truth table, the Boolean function and the
  logic circuit for half adder are
• S xy xy ( from the truth table)
• C xy ( from the truth table)

x
y
S
x
y
C
x
y
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• Also by looking at truth table, half adder can be
  implemented by an exclusive-OR and a AND gate.
• Sxy xy x y
• C xy
• So the alternative circuit for half adder is

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• Full Adder
• A full adder is a combinational circuit that
  forms the arithmetic sum of three bits.
• It consists of three inputs and two outputs
• Two of the inputs are x and y, representing the
  two significant bits to be added.
• The third input z is carry from the previous
  lower significant position.
• Two output are sum(S) and carry(C)
• the truth table and map for full adder are
• S xyzxyzxyzxyz C xyxzyz
• C xyxyzxyz (not completely simplified)

y
y
yz
yz
11
01
00
10
11
01
x
00
10
x
0
0
x
1
1
x
z
z
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• The logic diagram of full adder can be
  implemented from expressions for sum(S) and
  carry(C)
• It also can be implemented from two half adders
  and one OR gate as shown below .
• Sz (x y)
• S z (xy yx)
• Sz(xyyx) z(xyyx)
• S zxyzyxz(xy).(yx)
• S ... z(xy).(yx)
• S zxyzyxzxy zyx
• ( the same as maps result)
• The carry output is
• C z(xy xy) xy
• C xyzxyz xy
• ( the same as maps result )

The S output from the first half adder with the z
are input for the exclusive OR for the second
half adder giving the below function for S.
The C output from the first half adder with the C
output from the second half adder ORed together
giving the below function for C
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• A binary adder is a digital circuit that produces
  the arithmetic sum of two binary numbers.
• It is implemented with full adders connected in
  cascade.
• For adding two n bit binary numbers (A and B) n
  full adders are used (one full adder for each
  two bits that need to be added).
• Consider adding two 4-bit binary numbers
• A 1011 and B 0011
• Which have been implemented in the circuit shown
  in the next slide
• The input carry C0 is the least significant
  position and must be zero.
• First adder gets the first bit of the two binary
  numbers, plus input carry (C0) and produce the
  sum (S0) and the carry (C1) which will be the
  input of the second adder.
• Second adder gets the second bit of the two
  binary numbers plus input carry C1 and produce
  the sum (S1) and the carry (C2) which will be the
  input of the third adder. And so on

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