A New Calibration Technique for Pipelined ADCs

1
A New Calibration Technique for Pipelined ADCs

• Behzad Razavi
• Electrical Engineering Department
• University of California, Los Angeles

Verma and Razavi, ISSCC09
2
Outline

• Pipelined ADC Architecture
• Calibration Algorithm
• Building Blocks
• Experimental Results
• Conclusion

3
Generic Pipelined ADC
l Relatively modular design. l Area and power
do not scale linearly with resolution.
4
1-Bit/Stage Architecture
Multiply-by-2 Stage
First Stage of Pipeline
5
Advantages of 1-Bit/Stage Architecture
almost exponentially
6
Nonidealities
l Op Amp Offset l Charge Injection Mismatch l
Comparator Offset l Capacitor Mismatch l Op Amp
Gain l Op Amp Input Capacitance l Op Amp
Nonlinearity l kT/C Noise
7
Concept of Residue
8
Residue in 1-Bit/Stage Architecture
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1.5-Bit/Stage Architecture
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Advantages of 1.5-Bit/Stage Architecture
SHA-less Arch.
l Comparator offset and input timing mismatch
are relaxed. l Op amp offset can be tolerated
? input and output of op amp need not be
shorted during reset.
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Errors Revisited
l Op Amp Offset ? l Charge Injection Mismatch
? l Comparator Offset ? l Capacitor Mismatch?
l Op Amp Gain? l Op Amp Input Capacitance? l
Op Amp Nonlinearity? l Op amp and kT/C Noise?
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Possible Approach

• Choose capacitors to satisfy kT/C noise, not
  matching.
• Choose op amp with high swing
• ? kT/C noise relaxed
• ? power consumption reduced.
• Choose best trade-off between speed, power, and
• noise of op amp regardless of its gain.
• Digitally correct for everything!
• For example,

• Assume
• - Open-loop op amp gain 25.
• - Resolution 10-12 bits.
• - Sampling rate 200-500 MHz.
• - Technology 90-nm CMOS.

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How to Calibrate?
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Effect of Nonidealities
Ideal
With Nonidealities
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Prior Art
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Philosophy of This Work
Observations

• Transistors are approaching trans-resistors.
• High-gain high-speed op amps are approaching
  extinction.

Our Approach

• Choose capacitors to satisfy kT/C noise, not
  matching.
• Choose op amp with high swing
• ? kT/C noise relaxed
• ? power consumption reduced.
• Choose best trade-off between speed power of op
  amp regardless of its gain.
• Digitally correct for everything!

17
System Architecture

• Foreground Calibration
• No Dedicated SHA
• Realized in 90-nm CMOS

18
Inverse Function
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Accuracy of 3rd-Order Model
Max. Error 0.15 LSB
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Calibration Algorithm (Stage j)
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Estimation of a1 and a3

• LMS routine adjusts a1 and a3 such that (Dcal
  Dtot)2 is minimized.

22
Simulated Convergence
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Estimation of wj

• Calibration routine adjusts wj such that Dcal -
  Dtot is minimized.

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Building Blocks

• Front-End Sampling Network
• High-Speed Low-Power Op Amp
• High-Accuracy Reference DAC
• Calibration Logic

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SHA-Less Front End

• Issues 1. Delay Mismatch and Skew
• 80 ps uses up 0.25 bits of redundancy
• 2. Sub-ADC Conversion Time

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Op Amp Topology

• Large Output Swing ? 2-Stage Op Amp
• Maximum Speed ? 2 Poles

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Op Amp Model (w/o Compensation)
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Simulated Op Amp Performance

• Open-loop Nonlinearity 2
• Open-loop Gain 25
• Phase Margin gt 60
• Settling Error lt 0.1 LSB

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High-Accuracy DAC

• Capacitor DACs
• Large units/area required to achieve high
  accuracy
• Current-Steering DACs
• Gain error and limited output swing
• Resistor-Ladder DACs
• Rail-to-rail swing
• Long settling time

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Resistor DAC Sources of Error
Non-silicided polysilicon for the ladder.
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Proposed Resistor DAC

• Four sizes fabricated and measured
• L 64 µm, 32 µm
• W 20 µm, 10 µm

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Measured INLMax Distribution
40 Samples

• 32 µm x10 µm

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Measured INLMax Distribution
40 Samples
64 µm x20 µm

• 64 µm x10 µm

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Calibration Logic
Gate Count 20000 Power 8 mW
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Die Photograph
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Core Layout
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Integral and Differential Nonlinearity
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SNDR vs. Input Frequency
fs 500 MHz
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Results
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FOM Comparison
8
Single Channel
Interleaved
7
2
6
4
5
3
1
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Temperature Sensitivity

• Mobility degradation at higher temperature
  changes the open-loop gain.
• With fixed bias current, op amp gain varies by
  10 for a 50C temperature change.
• Variation in a1 1
• Still an issue at 10-bit level
• Constant overdrive voltage biasing suppresses
  the a1 variation.
• SNDR degradation is limited
• to 2 dB in simulation

Yoshioka et al., ISSCC, 2007
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Conclusion

• A new calibration technique is proposed to allow
  use of high-speed, low-power yet inaccurate op
  amps in pipelined ADC.
• A new resistor ladder DAC with 11 bits of
  linearity is demonstrated.
• A prototype ADC employing these techniques
  operates at a sampling rate of 500 MHz and
  digitizes a 233 MHz signal with 52.8 dB SNDR
  while consuming only 55 mW.

43
Acknowledgement

• This research was supported by Realtek
  Semiconductors, Kawasaki Microelectronics, and
  Skyworks Inc.
• Fabrication was kindly provided by TSMC.

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References

• 1 S.-C. Lee et al., A 10b 205MS/s 1mm2 90nm
  CMOS Pipeline ADC for Flat-Panel Display
  Applications, Solid-State Circuits Conference,
  2007.
• 2 C.C.Hsu et al., An 11b 800MS/s
  Time-Interleaved ADC with Digital Background
  Calibration," Solid-State Circuits Conference,
  2007.
• 3 S. M. Louwsma et al., "A 1.35 GS/s, 10b, 175
  mW Time-Interleaved AD Converter in 0.13 µm
  CMOS," VLSI Circuits, 2007 IEEE Symposium on,
  June 2007.
• 4 S. Gupta et al., A 1GS/s 11b
  Time-Interleaved ADC in 0.13µm CMOS, Solid-State
  Circuits Conference, 2006.

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References

• 5 H.-C. Kim et al., A 30mW 8b 200MS/s
  Pipelined CMOS ADC Using a Switched-Opamp
  Technique, Solid-State Circuits Conference,
  2005.
• 6 K-W. Hsueh et al., A 1V 11b 200MS/s
  Pipelined ADC with Digital Background Calibration
  in 65nm CMOS, Solid-State Circuits Conference,
  2008.
• 7 B. Hernes et al., A 92.5mW 205MS/s 10b
  Pipeline IF ADC Implemented in 1.2V/3.3V 0.13 µm
  CMOS, Solid-State Circuits Conference, 2007.
• 8 B. Hernes et al., A 1.2V 220MS/s 10b
  Pipeline ADC Implemented in 0.13µm Digital CMOS,
  Solid-State Circuits Conference, 2004.