FE8113

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FE8113 High Speed Data Converters
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Part 2 Digital background calibration
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Stewart Clark, Broken english spoken perfectly
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Papers 7 and 8
K.El-Sanakry, M.Sawan A New Digital Background
Calibration Technique for Pipelined ADC,
Proceedings of the 2004 International Symposium
on Circuits and Systems, 2004. ISCAS '04, Vol.
1,  23-26 May 2004, pp I-5 - I-8 B.Murmann,
B.E.Boser A 12-bit 75-MS/s Pipelined ADC Using
Open-Loop Residue Amplification, IEEE Journal of
Solid-State Circuits, Vol. 38, No. 12,  December
2003, pp2040-2050
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K.El-Sanakry, M.Sawan A New Digital Background
Calibration Technique for Pipelined ADC

• Outline
• Compensation of finite opamp dc gain
• By transforming the ADC to parallell ADCs and
  measuring the gain ratios between different
  configurations ...

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K.El-Sanakry, M.Sawan A New Digital Background
Calibration Technique for Pipelined ADC
Radix 2 and Radix lt2 MDACs
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K.El-Sanakry, M.Sawan A New Digital Background
Calibration Technique for Pipelined ADC

• If ratios G1,radix2/G2.radix2 and
  G1,radixlt2/G2,radixlt2 are known, x and A can be
  computed

Calculation of finite dc gain parasitics
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K.El-Sanakry, M.Sawan A New Digital Background
Calibration Technique for Pipelined ADC
Calibration system, swaps between two gain
configurations
It should be noted that config 1 and config 2
refers to different n on previous slide, not
different radix
M 2
Can be drawn as a time interleaved ADC
Calibration method
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K.El-Sanakry, M.Sawan A New Digital Background
Calibration Technique for Pipelined ADC
TIADC Theory Gain mismatch between two paths
leads to inband image at kfs/2 - fin
The spectrum of digitized output Vgd of Vg is
given by
Time-Interleaved Theory
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K.El-Sanakry, M.Sawan A New Digital Background
Calibration Technique for Pipelined ADC
Choppes digitized output, multiplies with a small
constant and integrate to get an estimate of
g1/g2. This ratio is used to modify g2 so the
image frequency dissapears. When the system has
converged g1/g2 G1,radix2/G2,radix2
Repeated with different configuration to get
G1,radixlt2/G2,radixlt2
Calibration System
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K.El-Sanakry, M.Sawan A New Digital Background
Calibration Technique for Pipelined ADC
MADC Implementation
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K.El-Sanakry, M.Sawan A New Digital Background
Calibration Technique for Pipelined ADC
Without Calib With Calib Unit
SNR 42 60.8 dB
ENOB 6.9 9.8 bits
SFDR 46 76 dB
Simulation results
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification

• Outline A digital background calibration
  technique as an enabling element to replace
  precision amplifiers by simple powerefficient
  open-loop stages. At Nyquist input frequencies,
  the measured signal-to-noise ratio is 67 dB and
  the total harmonic distortion is 74 dB. The IC
  consumes 290 mW at 3 V and occupies 7.9 mm2.

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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Based on W. Yang, D. Kelly, I. Mehr,M. T. Sayuk,
and L. Singer, A 3-V 340-mW 14-b 75-Msample/s
CMOS ADC with 85-dB SFDR at Nyquist input, IEEE
J. Solid-State Circuits, vol. 36, pp. 19311936,
Dec. 2001.
Architecture
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Conventional closed loop architecture is replaced
with an open loop transconductance driving a
resistance
Conventional vs Open Loop
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Assuming square law transistors and memoryless
nonlinearities
VOV is gate overdrive, ?ß/ß is current mismatch
between transistors
Non-linearity model
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
With Vx-pp 250mV, choose VOV gt 250mV to get low
second and fifth order distortion. 3rd order
distortion is unavoidable and is compensated for
digitally. Shown below is the equivalent model
Cubic distortion
Offset in amplifier
Offset in SADC
Gain error in amplifier
Error model
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Offset in SADC and DAC extra redundancy in
second stage Gain error corrected using
previously described techniques A. Karanicolas
et al., A 15-b 1-MSample/s digitally
self-calibrated pipeline ADC, IEEE J.
Solid-State Circuits, vol. 28, pp.
12071215, Dec. 1993. The new technique is the
approach to cubic distortion correction
Through inversion of the of the overall cubic
polynomial with gain compression (a3 lt 0 )
Nonlinearity correction
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Since the backend ADC quantize Vres1 the
nonlinearity can be corrected by operating on the
backend code. This assumes that the backend
error, eb, is small.

• Components of eb
• Linear and nonlinear or code dependent errors
  must be kept small by design
• Static input-referred offset comparator
  redundancy and digital correction arithmetic
• Quantization noise two redundant bits

Backend ADC requirements
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Switches between distinct overlapping residue
functions. Digital linearity correction operates
on both residues (p2). Measure h1 and h2 , if h1
h2 then we have perfect adjustment of residues
into straight lines. If h1 gt h2 we have
incomplete nonlinearity error cancellation.
Nonlinearity detection
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Uses signal statistics to determine h1 and h2.
Requires well behaved probability density
function. Generates cumulative histograms for
digital backend conversion results
Nonlinearity estimation
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Correction architecture
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification

• Sub-DAC must be linear, nonlinearity only present
  in gain stage
• Needs a busy signal around which the distance
  estimates (h1 and h2) is measured. Inactivity can
  be detected, thus miscalibration can be avoided.
  Activity spanning 1/16th of the fullscale range
  is sufficient for calibration
• Tradoff between accuracy and tracking speed of
  LMS method

Calibration Limitations
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Cascode devices used to improve PSRR Pi-load used
to decouple choice of common mode output level
from differential gain requirements Replica tail
biasing used to improve CMRR GmR replica bias
reduce sensitivity to ambient temperature changes
1 Stage implementation
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B.Murmann, B.E.Boser A 12-bit 75-MS/s Pipelined
ADC Using Open-Loop Residue Amplification
Yang01
Murmann03
Measured performence