FE8113

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FE8113 High Speed Data Converters
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Part 1 Architectures

• First three chapters of van de Plassches
  textbook
• Ch.1 The Converter as a black box
• Ch.2 Specifications of converters
• Ch.3 High-Speed A/D Converters

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Chapter 3High-speed A/D Converters
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Design problems in high-speed converters

• Timing errors
• Sampling clock jitter
• Limited rise/fall time of sampling clock
• Skew of the clock and input signal at different
  places on the chip
• Typically a signal travels 200µm-300µm in 1ps
  (1/3 the speed of light)
• Signal-dependent delay
• An amplitude limiting circuit followed by a
  bandwith-limiting circuit will introduce
  slope-dependent delay
• Leads to 3rd order distortion at the quantizer
  output

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Design problems in high-speed converters

• Distortion
• Sampling comparators aperture time
• High-frequency sampling errors, averaging effect
  in time domain
• Leads to third order distortion
• Distortion in the input buffer or input signal
  amplifier
• Harmonics and mixing products of the input signal
• Offset in input amplifiers and comparators
• Changes in the reference voltage values
• Delays of analog signal and clock signal

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Full-flash converters

• 2N-1 reference voltages and comparator stages
• Well suited for high speed, low resolution ADCs
• Drawbacks (for medium N)
• Large, nonlinear input capacitance
• Area and power consumption 2N
• Large kickback to driving circuitry
• May need off-chip buffers and clock drivers

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Interpolation

• Interpolation reduces the number of input
  amplifiers and reference levels
• Additional zero crossings obtained by passive or
  active interpolation

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Interpolation

• Interpolation has a positive effect on DNL
• The good matching of resistors result in
  high-accuracy interpolated signals with small DNL
  errors

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Multiple interpolation

• Multiple interpolation will reduce the number of
  references and amplifiers even more
• But
• As the resistor string grows, the middle of the
  string will have a larger time constant compared
  to the edges
• Results in increased power at the amplifier
  outputs, and low value for Rintpol

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Active interpolation

• With passive, resistive interpolation the
  amplifier output impedance must be kept low.
  Otherwise there will be an interaction between
  interpolating stages
• A way of overcoming this is active interpolation,
  which shows no interaction between interpolating
  stages

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Averaging

• Reduces sensitivity to offset voltages at input
  amplifiers
• A rough estimate is that the offset voltage
  reduces with a factor (Nactive)1/2
• SNR is improved by the same amount
• The figure shows improved linearity performance
  after averaging

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Averaging

• Near the ends of the averaging cahin, an unequal
  number of averaging amplifiers contribute from
  each side
• This results non-linearity, and in practice only
  70 of the input range is usable
• A solution to this is to increase the number of
  averaging levels, but this causes an inefficient
  system

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Averaging, non-linearity compensation

• To compensate for non-linearity errors, the end
  resistor are weighted differently, and the end
  signal is connected to the inverted input side of
  the resistor string
• Gives a continuous ring of resistors
• Active averaging
• One extra pair at each end will give ideal
  linearity compensation
• Matching problems, however, will influence the
  offset and linearity of the system

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Gray code full flash converters

• With input signal increasing 1LSB, only one
  comparator changes state
• Cross-coupling of comparators, for 4 bits
• MSB Level 8
• MSB-1 Levels 4 and 12
• MSB-2 Levels 2,6,10 and 14
• LSB Levels 1,3,5,7,9,11,13 and 15
• Analog encoding of signals is performed by
  differential pairs
• Small amount of clocked comparators, resulting in
  small area and power consumption
• Difference in comparator delay will lead to
  coding errors and distortion unless there is a
  sample-and-hold at the input
• Encoding comparator structure grows towards LSB,
  limiting bandwith
• Two-step encoding is possible. The result is
  formed by a logical combination at the output

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Circular code full flash converters

• Same principle as for gray-converter, except
  circular code will give equal comparator loading
• In circular code, each bit, except the MSB, has
  the same number of transistions from the lowest
  to the highest code
• Reduction in the number of comparators by at
  least a factor two

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Two-step flash converters

• Coarse and fine sub-converters
• Often, the full-scale range of the fine converter
  is increased with respect to the LSB step size of
  the coarse system
• Compensates for error between coarse and fine
  conversion

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Sub ranging converter architecture

• Basically a two-step converter with no gain stage
  between the coarse and fine converter
• Matching problems between gain stages and
  reference voltage ladders are avoided this way
• Reference ladder with 2N-1ladder taps
• 2N1 coarse ladder taps
• 2N2-1 fine ladder taps between each coarse ladder
  tap

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Pipeline converter architecture

• The pipeline ADC will be discussed in detail in
  Part II of the course

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Folding converter system

• Analog preprocessing transform the input signal
  into a repetitive output signal
• Same comparators used for multiple zero-crossings
  at the folding circuit output
• Low component count results in area and power
  saving
• Drawbacks
• High internal frequencies in folding circuit
• Loss of resolution due to limited bandwith in
  folding circiut

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Folding converter system

• Current-folding A/D converter system example
• Increasing Iin will forward bias an increasing
  number of diodes in the signal chain
• The crosscoupling of transistors to the output
  produces the folding function

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Folding converter system

• With limited bandwith in the folding circuit, the
  triangular shape of the folding function cannot
  be maintained
• This leads to missing codes and distortion

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Folding converter system

• High-frequency limitations can be overcome by a
  double folding system
• Two sets of cross-coupled differential pairs
  connected to a reference ladder
• Two folded outputs with a phase shift of 90o
• Switch between the two, so that you always
  operate in the linear region

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Folding converter system

• High-frequency performance increased by adding a
  T/H at the input
• High requirement for the T/H amplifier
• Distributed T/H (one for each folding block)
• Relaxes the T/H amplifier requirements

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Folding converter system

• Cascaded folding
• Cascaded sets of folded output signals
• Two-step folding
• N signals from analog preprocessor
  (amplifierreferences) are combined and folded
• The outputs from N folding blocks are combined in
  the next stage

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Folding converter system

• Cascaded folding
• Cascaded sets of folded output signals
• Two-step folding
• N signals from analog preprocessor
  (amplifierreferences) are combined and folded
• The outputs from N folding blocks are combined in
  the next stage

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Delay over interconnect lines

• Special attention must be paid to layout of clock
  and signal lines
• Delay line modeled as a distributed RC-network
• A tree structure gives the same time constant to
  each comparator

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Discussion...