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Introduction to gain error calibration and test signal injection in pipelined ADCs ... S.Sonkusale, J.Van der Spiegel: 'Mixed-Signal Calibration of Pipelined Analog ...
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Serial to parallel conversion - Data latched out by latch clock ... In an ideal converter system the maximum analog bandwidth is equal to fs/2. ERB ...
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Incomplete settling in f2 = errors in interstage gain Gi and DASC gain Ki ... Interstage gain-error transformed to ADC gain error by moving GE to output of DASC ...
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TIADC Theory: Gain mismatch between two paths leads to inband image at kfs/2 - fin ... Replica tail biasing used to improve CMRR ...
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Skew of the clock and input signal at different places on the chip ... Small amount of clocked comparators, resulting in small area and power consumption ...
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... recalculating the digital output based on each stage's equivalent radix. The equivalent radices are extracted in the background by using a digital correlation ...
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