Digital VLSI Design

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Digital VLSI Design

• Full Automation
• Maximum benefit of scaling
• High speed ,low power

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Other logic design styles

• Switch logic

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Pass Transistor Logic
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Level restoration
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Swing Restored Pass Logic
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TRANSMISSION GATE
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Mux
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TG Xor
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DELAY OF N TRANSMISSION GATES
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REPEATERS
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Static Gates In Synchronous design
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Wire delays
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Electromigration (1)
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Impact of Interconnect Parasitics
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When to Consider Transmission Line Effects?
tr/tf gt 5 t flight lumped model
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Interconnect Delay with Inductive Effects

• For the design of critical performance nets (such
  as clock distribution) on a processor chip,
  inductance must be taken into consideration
• Simulation result in (b) shows the effect of
  ringing on a rising transition due to reflections
  at a discontinuity on an inductive net
• Additional delay due to settling time is incurred
  if such ringing can not be eliminated by proper
  transmission line design techniques

B
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Nature of Interconnect
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INTERCONNECT
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Wire Resistance
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Dealing with Resistance
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Resistance of a Wire (Rectangular Geometry)

• Resistance of a uniform slab
• R ? (l/A) (?/t) (L/W) where ? is the
  resistivity in ohm-cm, t is the thickness in cm,
  L is the length, W is the width, and A is the
  cross-sectional area
• Using the concept of sheet resistance, R
  Rs (L/W) where Rs is called the sheet
  resistance and given in ohms per square
• Rs ? / t
• Apply to metal wire, poly line, or even a
  diffused P or N area of sufficient length
• Resistance of an FET transistor (linear)
• R Vds/Ids 1/?(Vgs Vt 0.5 Vds)
• As Vds ? 0,
• Rds ? 1/?(Vgs Vt) k(L/W)
• where k 1/?Cox(Vgs Vt)

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Polycide Gate Mosfet
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INTERCONNECT
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Capacitance The Parallel Plate Model
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Capacitance of the Interconnect Metal Wires

• For wide conductors with W gtgt H, capacitance to
  substrate (of any ground plane) can be determined
  as a parallel plate capacitor
• C ?A/t where A is the planar area of
  the wire and t is the thickness of the oxide
• For most real conductors in todays IC
  technology, fringing fields contribute a major
  part of the line capacitance and must be included
  in the capacitance calculations.
• For W H (below), fringing fields add more than
  the parallel plate portion to the total line
  capacitance.!

R. W. Knepper SC571, page 4-15
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Fringing Capacitance
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Interwire Capacitance
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Metal Line Capacitance with Fringing Effect

• Solution by Yuan and Trick given at right assumes
  the wire can be approximated by a piece of metal
  with thickness t and two rounded edges
• parallel plate portion with width equal to W
  t/2
• fringing term due to two hemispherical ends with
  exact solution to field equation
• Example for wire of width W0.30 um, thickness t
  0.30 um, and dielectric thickness h 0.35 um,
  gives a result
• C 0.13 fF/um
• where the fringing part is over ¾ of the
  total capacitance.

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Fringing Capacitance Values
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Capacitance of Layered Multiple Conductors

• Structure of Interconnect
• Layers 1 and 3 run along page
• each can be assumed to act as a ground plane
  (solid plane)
• Layer 2 runs out of the page
• Equivalent capacitances per unit length
• Ctotal C21 C23 2 x C22
• C21 is from center conductor to lower ground
  plane (layer 1)
• C23 is from center conductor to upper ground
  plane (layer2)
• C22 is from center conductor to adjacent wire on
  the right
• C22 also occurs from center conductor to adjacent
  wire on right assuming spacings are symmetrical
• Equations at left give capacitance from center
  conductor to one or both ground planes

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Capacitance of Layered Multiple Conductors

• Equations at left give capacitance per unit
  length between center conductor and adjacent
  conductor (C22) for both cases
• One ground plane only (layer 1)
• Two ground planes (layers 1 2)
• Parameters
• T wire thickness
• H interlayer dielectric thickness
• S wire spacing
• W wire width

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Interconnect Cross-section for Dual Metal, Single
Poly System
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IDEAL WIRE

• No impact on electrical behaviour of circuits
• Whole wire is an equi-potential region

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INTERCONNECT DELAY Realistic Wire Models

• Lumped RC Delay Model
• T Network RC Delay Model
• Ladder Network Model
• Elmore Delay Model

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LUMPED C DELAY MODELif wire resistance small and
frequency is small
Vout VDD (1 e t / RONCL )
Vout VDD (e t / RONCL )
tphl / tpLH 0.69 RC
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Lumped RC-ModelsInaccurate estimate
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Tree RC-Models
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T-network Delay Model

• Star-delta-transformation
• VoutZAB/(ZABZBC)
• Vout(2/RC)/(S2/RC)(1/S)
• (1/s)-1/(s2/RC)
• U(t)1-exp(-2/RC)t
• FOR V50
• tp(RC ln2)/20.35 RC

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LADDER NETWORK RC-Delay
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THE ELMORE DELAY MODELmultiple branches- single
input

• For a step input Vin, the delay at any node can
  be estimated with the Elmore delay equation
• tDi ? Cj ? Rk
• For example, the Elmore delay at node 7 is give
  by
• R1 (C1 C2 C3 C4 C5 C6C7C8) (R6)
  (C6C7C8) (R7) (C7 C8)

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Elmore delay model for (Distributed RC) Ladder
Network

• Delay in a distributed RC ladder network is given
  by
• ?n ½ R C n (n1)
• where R and C are the series resistance and
  nodal capacitance for each section, and n is the
  number of sections.
• For n large, the above expression reduces to
• ? ½ r c l2
• where r and c are the resistance and
  capacitance per unit length, and l is the total
  length of the wire.
• Note that interconnect delay is proportional to
  the square of wire length.

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Reduction of wire delay
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Use of a Buffer Amplifier in a Long Line to
reduce delay

• Buffers may be used in long lines to reduce the
  total line delay
• Non-inverting line driver circuit having an
  intrinsic delay ?buf
• Total line delay becomes ½ rcl12 ?buf ½
  rcl22 where l1 is the first line segment and l2
  is the second line segment (l1 l2 l)

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Minimize delay
Reduction in overall line delay is achieved If
interconnect delay is to be negligible or ? w
?buf or 0.7 x ½ rcl2 ?buf where l is the
line segment length l ltlt v (2 ?buf / 0.7 rc)
--- upper bound
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• Example
• What is the intrinsic wire delay of a 0.18 um
  CMOS technology minimum Cu wire on level M2 with
  length 10 mm, thickness 0.3 um, width 0.3 um and
  height 0.35 um above a M1 ground plane with SiO2
  dielectric (neglecting M3 and above)?
• r ?/A 24 ohm-um/(0.3 um x 0.3 um) 0.266
  ohms/um
• c 0.13 fF/um from equation on slide 4-11
• ? ½ rcl2 0.5 x 0.226 ohms/um x 0.13 fF/um x
  (10,000 um)2 1.4 ns
• How much will the delay become if a buffer with a
  200 ps delay is inserted in the line center?
• ? 2 x (¼ x 1.4 ns) 200 ps 0.9 ns

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Reducing RC-delay
Repeater
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Example---clock distribution network with
repeaters
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Model for Distributed RC Line with Capacitive Load
RW
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• A simple model for a distributed RC interconnect
  wire can be represented as shown at left
• driver circuit with equivalent Rdrvr
• Receiver circuit with capac load Cload
• Interconnect with total resistance Rwire and
  total capacitance Cwire
• The total delay of the wire and load can be
  written as
• ?t (Rdrvr Rwire)(Cwire Cload) ½ RwireCwire
• The equivalent circuit at the bottom left gives
  identical result to above RC model given that
  delay ? ½ rcl2
• ½ RwireCwire
• RS Rdriv, CtCwire CL

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Including all parasitics, make simulation slow
and design optimization tedious
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For Easy Analysis of interconnects

• Ignore inductive effects if resistance of wire is
  substantiale.g long aluminum wire
• Ignore inductive effects if tr / tf is very large
• For short wire, ignore resistances
• Ignore inter-wire capacitance if wires run
  together for short distance

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Efficient Interconnect hierarchy
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Complex logic gatesGATE LOGIC

• NAND
• NOR
• EXOR

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DYNAMIC LOGICyields SYNCHRONOUS DESIGN
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How long charge can remain stored at soft node?
Soft node
Is dynamic logic feasible as output is remaining
in tristate condition. Will it cause data to get
lost?
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Worst case hold time
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Worst case hold time
Vm
V omax
So charge leakage required time im
ms. Sufficiently large By that time, data would
remain logic1 and would have been used
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PRECHARGE EVALUATE LOGIC
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Precharge/ evaluation

• Clk0 precharge
• Output charges
• Clk1 evaluation
• Output conditionally discharges

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Salient features

• Non Ratioedonly one path is on at a time
• Inverting Logic
• Less Transistors
• No glitches (Only 1?0 Transition)
• Low Input Cap.

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Power issues

• Power dissipated by clk circuit is huge
• Power dissipated by gate is less

lt
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Problems

• Charge sharing, degraded logic levels
• Charge leakage
• Tphl moreextra evaluation transistor in chain

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Charge Sharing, Leakage
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Remedy For Charge Sharing, Leakage
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Voh Degradation
- ½ Vdd
If CL
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Cascading problem in dynamic--leads to
malfunctioning circuit
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Problem-

• Output tri-stated in evaluation phase
• B1, A 1?0,
• A cannot change instantaneously
• So Vout starts discharging
• Voh gets degraded

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Precharge/ evaluation

• Clk0 precharge
• Output charges
• Clk1 evaluation
• Output conditionally discharges

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Example
Expected output
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Remedy 1domino CMOS
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DUAL RAIL DOMINO/ CLKED DCVSL
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Example--- A.B C.DE
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ADVANTAGE1 --MULTIPLE OUTPUT DOMINO
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Example
Multiple precharge trans.
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ADVANTAGE2COMPOUND DOMINO
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REMEDY ---NP CMOS logic
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Single cycle operation
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Example--- A.B C.DE
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4-bit Adder design
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NP CMOS-pipeline implementation Multiple cycle
operation
CLK
CLK
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Pipelined implementation-requires latch in
between to store data
To save output
To latch input
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TSPC modified NP DOMINO WITH STORAGE ELEMENTS
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TSPC
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Appendix
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Driving Large Capacitances
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Using Cascaded Buffers
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design

• Determine N, u
• cLun1 cg
• (n1)ln (cL/cg) / ln(u)
• Delayto (cdu cg) / (cdcg)
• Delay total (n1) to (cdu cg) / (cdcg)
• Delay total ln (cL/cg) / ln(u)
• to (cdu
  cg) / (cdcg)
• u(ln u-1) (cd/cg) 0
• U e

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tp as function of u and x
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Impact of Cascading Buffers
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Output Driver Design