Why carry lookahead

1
Why carry lookahead?
c0
CarryIn CarryOut
a0
Result0
b0
c1
CarryIn CarryOut
a1
Result1
b1
The most significant bit of sum must wait for the
sequential evaluation of all 32 1-bit adders.
Its quite slow!
c2
c31
CarryIn
a31
Result31
b31
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CarryIn Formula
ci
CarryIn CarryOut
ai
Result i
bi
ci1
CarryIn CarryOut
ai1
Result i1
bi1
carry-out f ( c-in, a, b ) ci1 cout (bi
ci) (ai ci) (ai bi) (ai bi)
(ai bi) ci (see the truth table in ALU
lecture)
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Fast Carry Using the First Level of Abstraction
Propagate and Generate
c1 (a0 b0) (a0 b0) c0 (see
formula, prev. pg.) c2 (a1 b1) (a1 b1)
c1 (a1 b1) (a1 b1) ((a0 b0)
(a0 b0) c0)
same pattern
ci1 (bi ci) (ai ci) (ai bi)
(ai bi) (ai bi) ci
generate gi gi ai bi
propagate pi pi ai bi
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Propagate and Generate (cont.)
Why is it called propagate and generate?
ci1 gi pi ci

• when gi 1, ci1 1, generate ci1
  independent of ci (ci1 1 pi ci 1)
• when gi 0 and pi 1, ci1 ci, propagate ci
  to ci1
• (that is, ci1 gi pi ci 0 1 ci ci)

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Propagate and Generate (cont.)
Carry-lookahead for 4 bits
c1 g0 (p0 c0)
c2 g1 (p1 c1) g1 (p1 g0) (p1
p0 c0)
c3 g2 (p2 g1) (p2 p1 g0)
(p2 p1 p0 c0)
c4 g3 (p3 g2) (p3 p2 g1) (p3 p2
p1 g0 ) (p3 p2 p1 p0 c0)
note only c0 needed
Lead to large equations, two levels of
abstraction are needed
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Fast Carry Using , using two Levels of
Abstraction
To form a 16-bit adder
First level 4-bit adder using the previous
carry-lookahead logic
Second level carry lookahead for the first level
4-bit adders
CarryIn
4-bit adder
Carry-lookahead
P0, G0
C1
4-bit adder
P1, G1
C2
4-bit adder
P2, G2
C3
P3, G3
4-bit adder
C4
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CarryOut
7
Generate a carry out of a 16 bit adder - collect
bit level p gs to adder-level P Gs
The higher level propagation signal Pi is true
only if each of the bits in the group will
propagate a carry.
P0 p3 p2 p1 p0 P1 p7 p6 p5 p4 P2
p11 p10 p9 p8 P3 p15 p14 p13 p12
note each term is (prop prev gen) G0 g3
(p3 g2) (p3 p2 g1) (p3 p2 p1
g0) G1 g7 (p7 g6) (p7 p6 g5) (p7
p6 p5 g4) G2 g11 (p11 g10) (p11 p10
g9) (p11 p10 p9 g8) G3 g15
(p15 g14) (p15 p14 g13)
(p15 p14 p13 g12)
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Carry out calculation
So the equations of the higher level carry in for
the lower level 4-bit group is similar to the
4-bit adder carry in equations
C1 G0 (P0 c0) C2 G1 (P1 G0) (P1
P0 c0) C3 G2 (P2 G1) (P2 P1 G0)
(P2 P1 P0 c0) C4 G3 (P3 G2)
(P3 P2 G1) (P3 P2 P1 G0)
(P3 P2 P1 P0 c0)
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Two levels of the Propagate and Generate
Given two 16-bit numbers, determine the values of
gi, pi, Gi and Pi, and the CarryOut15(C4).
b 0010 0001 1100 0010
a 1011 0010 1010 1101
a 1011 0010 1010 1101
Align the bits
b 0010 0001 1100 0010
First level abstraction
gi 0010 0000 1000 0000
calculate gi (ai bi) and pi (ai bi)
pi 1011 0011 1110 1111
Bits are numbered 15 to 0 from left to right
Second level abstraction
P3 1 0 1 1 0
P3 p15 p14 p13 p12
P2 0 0 1 1 0
P2 p11 p10 p9 p8
P1 p7 p6 p5 p4
P1 1 1 1 0 0
P0 p3 p2 p1 p0
P0 1 1 1 1 1
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a 1011 0010 1010 1101
b 0010 0001 1100 0010
gi 0010 0000 1000 0000
pi 1011 0011 1110 1111
Bits are numbered 15 to 0 from left to right
G0 g3 (p3 g2) (p3 p2 g1) (p3 p2
p1 g0)
G0 0 (1 0) (1 1 0) (1 1 1 0)
0
G1 g7 (p7 g6) (p7 p6 g5) (p7 p6
p5 g4)
G1 1 (1 0) (1 1 0) (1 1 1 0)
1
G2 g11 (p11 g10) (p11 p10 g9) (p11
p10 p9 g8)
G2 0 (0 0) (0 0 0) (0 0 1 0)
0
G3 g15 (p15 g14) (p15 p14 g13) (p15
p14 p13 g12)
G3 0 (1 0) (1 0 1) (1 0 1 0)
0
CarryOut15 is C4 G3 (P3 G2) (P3 P2
G1) (P3 P2 P1 G0) (P3 P2 P1 P0
c0)
C4 0 (0 0) (0 0 1) (0 0 0 0)
(0 0 0 1 0) 0
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Compared to ripple adder

• Ripple adder wait for carries to ripple through
  all 32 1-bit adders
• Carry lookahead adder carry lookahead through
  two levels abstraction, which provides faster path

The gate delays for the critical paths of two
16-bit adders
Ripple adder 16 2 32 (where carry out
signal takes two gate delay per bit)
Carry lookahead adder 2 2 1 5
First level pi and gi is OR or AND of ai and bi,
which takes 1 gate delay.
Second level Pi is AND of pi, and Gi is
specified in two levels using pi and gi, so the
worst case takes 2 gate delay
Final CarryOut C4 is specified in two levels
using Pi and Gi, and the worst case takes 2 gate
delay
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References

• John L. Hennessy and David A. Patterson, Computer
  Organization and Design, The Hardware/Software
  Interface, 2nd Edition, Morgan Kaufmann
  Publishers, Inc., 1998