Multiprocessors on FPGAs

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Multi-processors on FPGAs

• Nilay Vaish
• Rajat Sahni
• Under the supervision of
• Prof. Kolin Paul
• Prof. M Balakrishnan

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Overview

• Resource Sharing and Synchronization
• FSL
• State Machine Design
• Integration with EDK
• Scripts
• Manual
• Architecture for Fast Fourier Transform
• Salient Features
• SVGA Display

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First Solution

• Bus Locking

Data Interleaving on UART
No interleaving, but resources blocked, bus locked
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Second Solution
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State Machine Design
Idle
Fsl1_exist
Read
MSB 0
MSB 1
Acquire
Release
Write
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Quad Processor System
Oct Processor System
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Synthesis Information
Less than 2 overhead for RSSA
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Initial Design Flow

• Generate a uniprocessor design.
• Generate the MHS and MSS files using the scripts
  (Command Line)
• Update the MHS and MSS scripts of the original
  design.

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Design Dialog Flow

• Design Dialog multiprocessor base system
  builder built in Qt.
• Generates MHS and MSS with address space
  (Graphical Interface)
• Resource sharing peripheral can be included
  optionally
• Project can be imported in EDK
• Requires Switching between EDK and design dialog

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Integrating with EDK

• Custom buttons available
• Map custom buttons to user executables
• Perl scripts to analyze MHS
• Add the resource sharing peripheral (RSSA)
• Generate the software driver for the RSSA
• Generate the addresses for different peripherals

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Software Driver
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MULTIPROCESSOR ARCHITECTURE
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Multi Processor Architecture

• Features of the Design
• Modular
• Scalable
• Flexible
• Low Communication Overhead
• Demonstrated with FFT implementation

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FOUR STEP ALGORITHM

• Let N N1 x N2
• X as matrix with N1 X N2 points.
• Compute the DFT of these N points using Four Step
  Algorithm
• Perform N1 DFTs of size N2 along the rows of X.
• Transpose X
• Element-wise multiplication with twiddle factors
• N2 DFTs of length N1 along the rows of X.

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Four Step algorithm - variation of classical
Cooley-Tukey algorithm.

• General DFT formula is
• Put n N1n2 n1 and k N2k1 k2

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Single Processor Figures
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Latency Throughput Figures
A speedup of by a factor of more than 3
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Timing Breakup
M0
S1
S2
M1
S3
S4
Clock Cycles
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Timing Breakup
M0
S1
S2
M1
S3
S4
Clock Cycles
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System Level Block Diagram
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SVGA controller Block Diagram
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