Registers and Counters

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Registers and Counters
Digital Systems contain various types of memory
that form together a memory hierarchy.
high
A counter is a register that goes through
a pre-defined sequence of states.
A single flip-flop is a special case of
a register.
high
Registers are small, yet fast memories close to
the data path. Apart from taking data in and out,
registers also have some additional data
manipulation capabilities.
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A simple register
4 D-type flip-flops positive edge triggered with
negative logic asynchronous reset or clear input.
Reading in data into the register is called
loading the register.
The loading is done in parallel if the four data
bits are loaded simultaneously with a common
clock.
symbol
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Register With Load Control

• Loading on each clock pulse is (often)
  undesirable
• More control needed

C follows clock if Load is high ?
clock skew
?

• This is called clock gating. Take care!
• What happens when 'Load' changes when the clock
  is low

Clock and Gated Clock are not perfectly
synchronized a flip-flop using Clock and a
flip-flop using Gated Clock dont get activated
at the same time.
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Better Register With Load Control

• Gating clock leads to clock skew there is a
  propagation time between
• the main clock and the C-inputs of various
  flip-flops, which are supposed to sense the same
  unique clock(t) in a clocked synchronous
  sequential circuit.
• Need some other mechanism

• When Load 0, FF content copied to itself (to
  get no-change!)
• Build registers from these
• General principle don't gate the clock!

Four times this structure to build 4-bit register
with parallel load
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The Shift Register

• Move bits laterally , west-to-east, east-to-west,
  north-to-south, south-to-north, or a combination
  of these, unidirectional or
• bi-directional.
• Principle chain flip-flops

Circuit
Symbol
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example the serial adder
Recall Parallel Adder
is not really parallel!
Carry ripples through roughly 2n gates
long propagation time.
We can do better!
Or, we can reuse a single FA Serial Adder
Idea Use shift registers to store intermediate
results.
How?
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Ignoring Registers
Parallel adder is CC
Serial adder is SC
Serial addition is also called Software Addition.
What about Power Dissipation?
We say that the parallel adder has its states in
space, the serial adder has its states in time.
A typical example of space-time trade-off.
More hardware faster.
Less hardware slower.
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Serie-Parallel and Parallel-Serie
Serial In, Parallel Out.
Parallel In, Serial Out.
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Bi-directional Shift Register
Here is an up-down (bi-directional) shift
register.
Function Table
If Qi Q0, then Qi-1 SI
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Counters

• Very useful device
• Produce time delay
• Example 1 second-clock, count to 60
  1 minute delay
• Control computation
• Example serial adder, add 16 bits
  count to 16
• Types of counters
• Asynchronous (ripple counter) simple, but
  troublesome
• Synchronous counters (best kind)
• Up, down, special counters
• Counters with different periods

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Counting Sequences
Counters go through prescribed sequence of states
upon application of input pulses (clock or other
signals).
Binary counter Binary counter
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Ripple Counter with T Flip-Flops
Recall T flip-flop
Have seen this before. Remember?
Features Simple Clock input from logic
circuits not quite clock synchronous
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Synchronous Counters
Clock goes to all flip-flops.
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Many more counters can be thought of.
Up-down counters can go both ways for k
0 step 1 to 7, or for k 7 step 1
to 0
increment
decrement
Counters with parallel load can be initialized
N 1 for k N step 1 to N7
parametrized
Example BCD counter.
Symbol
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Designing Counters
Input Equations D(A) A B (m3 is x) D(B)
C D(C) B C
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Register Transfer
Basic Digital Systems consist of

• a datapath ? performs operations on data
• a control unit ? determines the sequence of
  operations
• one or more levels of memory ? caches

Datapaths consists of

• registers ? small and fast memories (basic
  components)
• operations performed on data in registers (load,
  clear, shift, count)

Registers ? elementary operation ? registers
register transfer operations Elementary
operations microoperations.
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Datapath
three registers can be active at the same time
2 (A,B) to read from, 1 (D) to write to all in
one clock cycle.
Buses
2 buses, bus A and bus B, n-bit wide. Mux B
selects between RF and Constant.
Function unit
Contains arithmetic/logic unit (ALU) and Barrel
shifter. FS is a function select code. Status
bits are Z (1 if result is all 0), N (sign) C
(carry) and V (overflow).
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Registers
R and PC are names of registers.
(or PC(158) and PC(70)
Transfer operations
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Register File Bus
Register transfer here is multiplexer based.
Bus based is another possibility
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Examble Memory transfer
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Function unit
Consists of an ALU and a Shifter.
Suppose ALU is
Micro operations
F
FS MFselect S2 S1 S0 Cin
F A?B, A?B, A?B.
F srB, slB
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With Shifter words can be shifted right or left ,
over one or more bits
Moving in a 0 at the most or least significant
bit position
or rotated
Entering outgoing bits at the other side (wrap
around)
The bidirectional shiftregister with parallel
load could be used.
Cost three clock pulses (load into SR, shift,
transfer to R)
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Micro operations
Arithmetic, logic and shift micro operations.
Logic plus (OR)
Microoperation OR
Meaning 1s complement, clear bits, set bits,
complement bits
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Control Word encoding.
Timing (simulation).
Depends on the complexity of the combinational
circuit parts.
Assume propagation delays of CC parts are small
with respect to clock period. This
means that status bits, Address out and Data out
(MB 0) change at the same time
as the register values.
Changes in registers as a result of a
microoperation appear at the clock cycle after
that in which the microoperation is specified.
(positve edge triggered FFs!)
Values of status bits, Address out and Data out
appear in the same clock cycle.
Values of Constant in and Data in are placed in
the clock cycle in which they are Needed.
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Pipelined Datapath
Suppose datapath design leads to a maximum clock
frequency of 83.3 Mhz, because
All to be done in one clock cycle of 12ns.
Introduce two extra registers (pipeline registers)
i.e, 2 extra ns.
All to be done in one clock cycle of 15ns? NO!
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No,
Because, due to pipeline registers, we can do
Write back of microinstruction k
(5ns) Execute of
microinstruction k 1 (5ns) Fetch
operand of microinstruction k 2 (5ns)
In the same clock period of 5 ns, which is at
200Mhz clock frequency
Clock period 1 2 3
4 (k) 5 (k1) 6 (k2) 7 8
Is 2.4 times as
Or throughput ( ?Ops/cc) many ?Ops.
is
2.4 as high.
In ideal case (neglecting filling/emtying) one
microinstruction/clock cycle, of 5ns, as compared
to one microinstruction/clock cycle of 12ns.