CS 140 Lecture 18

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CS 140 Lecture 18

• Professor CK Cheng
• 12/3/02

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Standard Sequential Modules

1. Register
2. Shift Register
3. Counter

3
3. Counter (Modulo-n counter)
D
CNT
TC
LD
CLK
CLR
Q
Q (t1) (0, 0, .. , 0) if CLR 1
D if LD 1 and CLR 0
(Q(t)1) mod n if LD 0, CNT 1 and CLR 0
Q (t) if LD 0, CNT 0 and CLR 0
TC 1 if Q (t) n-1 and CNT 1
0 otherwise
4
Given a mod 16 counter, construct a mod-m counter
(1 lt m lt 16) with AND, OR, NOT gates
Q3 Q2 Q1 Q0
m 6
3 2 1 0
CLR
CLK
CNT
X
D3 D2 D1 D0
LD
Q1
0 0 0 0
Q0
Set LD 1 when X 1 and (Q3Q2Q1Q0) (0101)
5
Given a mod 16 counter, construct an a-to-b
counter (0 lt a lt b lt 15)
5 to 11
Q3 Q2 Q1 Q0
CLR
CLK
CNT
X
D3 D2 D1 D0
LD
Q3
0 1 0 1
Q1
Q0
Set LD 1 when X 1 and (Q3Q2Q1Q0) b (in
this case, 1011)
6
Given a mod 16 counter, construct a counter with
sequence 0 1 5 6 2 3 7
Q2 Q1 Q0
CLR
CLK
CNT
X
D2 D1 D0
LD
Q2
Q0
Q0 Q1 Q0
Q2
Q0
When Q 1, load D 5 When Q 6, load D
2 When Q 3, load D 7
7
Q2 0 0 0 0 1 1 1 1
Q1 0 0 1 1 0 0 1 1
Q0 0 1 0 1 0 1 0 1
LD 0 1 0 1 - 0 1 0
Id 0 1 2 3 4 5 6 7
D2 - 1 - 1 - - 0 -
D1 - 0 - 1 - - 1 0
D0 - 1 - 1 - - 0 1
K Mapping LD and D, we get
LD Q2 Q0 Q2Q0
D2 Q0 D1 Q1 D0 Q0
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Sequence 0 2 3 4 5 7 6
Q2 0 0 0 0 1 1 1 1
Q1 0 0 1 1 0 0 1 1
Q0 0 1 0 1 0 1 0 1
LD 1 - 0 0 0 1 1 1
Id 0 1 2 3 4 5 6 7
D2 0 - - - - 1 0 1
D1 1 - - - - 1 0 1
D0 0 - - - - 1 0 0
LD 1 D 2 When Q(t) 0 LD 1 D 7 When Q(t)
5 LD 1 D 6 When Q(t) 7 LD 1 D 0 When
Q(t) 6
K Mapping LD and D, we get
LD Q2 Q1 Q2Q0 Q2 Q1
D2 Q0 D1 Q1 Q0 D0 Q1Q0
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Cascade Counter
Q7,Q6,Q5,Q4
Q3,Q2,Q1,Q0
CNT LD
CNT LD
X
TC
TC
CLK
CLK
D7,D6,D5,D4
D3,D2,D1,D0
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TC 1 when X 1, (Q3,Q2,Q1,Q0 ) (1,1,1,1)
(Q7 (t1) Q6 (t1) Q5 (t1) Q4 (t1) ) (Q7 (t)
Q6 (t) Q5 (t) Q4 (t) ) 1 if TC 1 X 1
The whole thing therefore can be viewed as a
modulo 256 counter.
0 1 2 3 4 13 14 15 0
1 2 3
(Q3,Q2,Q1,Q0 )
0 0 0 0 0 0 0 1 0
0 0 0
TC
(Q7,Q6,Q5,Q4 )
0 0 0 0 0 0 0 0 1
1 1 1