Lecture 11 Signal Integrity for Nanometer Design

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Lecture 11Signal Integrity for Nanometer Design
Professor Lei He EE 201A, Spring
2004 http//eda.ee.ucla.edu
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Outline

• Capacitive noise
• Technology trends
• Capacitance model and characteristics
• Layout optimization
• Inductive noise and layout optimization
• When inductance become important
• Inductance model and characteristics
• Layout optimization
• Example SINO algorithm for both Cx and Lx noise
• Other noise sources

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Interconnect Capacitance
Cx
Cf
Ca
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Significance of Coupling Capacitance
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Delay Variations Due to Coupling Capacitance
Cx
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Coupling Noise
Coupling noise from two adjacent aggressors to
the middle victim wire with 2x min. spacing.
Rise time is 10 of project clock period.

• Capacitive coupling depends strongly on both
  spatial and temporal relations!

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Solution to Capacitance Computation

• Accurate solution to small structure
• Numerical method based on Maxwells equations
• Raphael RC3, FastCap Nabors-White, TCAD91
• Efficient solution to full chip
• Using tables or empirical formulas
• 2.5-D capacitance model Cong-He-Kahng-et
  al,DAC97
• Capacitance is not simply A/d
• A area
• d distance

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Characteristics of Coupling Capacitance

• Coupling capacitance virtually exists only
  between adjacent wires or crossing wires

• Capacitance can be pre-computed for a set of
  (localized) interconnect structures
• 2D or 2.5D capacitance model

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Layout to reduce impact of Cx

• Noise avoidance technique
• Shield insertion
• Shield is a wire directly connected to Vdd or Gnd

Vdd
Gnd
s1
G
s2
s3
s4
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Timing Sensitivity

• Two nets are considered sensitive if a switching
  event on signal s1 happens during a sample time
  window for s2

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Layout to reduce impact of Cx

• Noise avoidance techniques
• Net ordering (track assignment / net placement)

Vdd
Gnd
s4
s1
s3
s2
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Characteristics of Coupling Capacitance

• Coupling capacitance is highly sensitive to
  spacing

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Relation between Delay and Noise

• T_max T ln (1/0.5-v) / ln 2
• T_min T ln (1/(o.5v) / ln 2
• Typical values
• V T_max/T T_min/T
• 0.1 1.32 0.74
• 0.15 1.51 0.62
• 0.20 1.75 0.52

AGG
AOUT
VOUT
VIC
VOUT w/o XTalk
delay
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Noise estimation and filtering

• Rule of thumb
• Cx/C lt threshold
• Devgan, ICCAD97
• V lt (Rv Rint / 2) Cx / (1.25 Tr)
• Tr rising time for the aggressor
• Vittal et al, TCAD99 (more accurate)
• V (Rv Rint / 2) Cx / 0.63Tr Ra (Ca Cx)
  Rv (Cv Cx) Rint Cx
• To reduce Cx impact
• Increase the driver size of victim
• Decrease the driver size of aggressor
• Or buffering
• Need a global device size solution coupled with
  Time Analysis

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Mini-Summary

• Capacitive crosstalk is localized
• Capacitive crosstalk affects both delay and
  signal integrity
• Capacitive crosstalk can be minimized by
• Spacing (and wire sizing)
• Device sizing
• Net ordering
• Shielding
• Buffering

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Outline

• Capacitive noise
• Technology trends
• Capacitance characteristics
• Layout optimization
• Inductive noise and layout optimization
• When inductance become important
• Inductance characteristics
• Layout optimization
• Example SINO algorithm for both Cx and Lx noise
• Other noise sources

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Is RC Model still Sufficient?

• Interconnect impedance is more than resistance
• Z ? R j?L
• ? ? 1/tr
• On-chip inductance should be considered
• When ?L becomes comparable to R as we move
  towards Ghz designs

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Candidates for On-Chip Inductance

• Wide clock trees
• Skews are different under RLC and RC models
• Neighboring signals are disturbed due to large
  clock di/dt noise
• Fast edge rate (100ps) buses
• RC model under-estimates crosstalk
• P/G grids (and C4 bumps)
• di/dt noise might overweight IR drop

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Inductance Minimization

• Reference plane
• wiring layers sandwiched between power planes

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Inductance Minimization

• Coplanar shields

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Characteristics of Coupling in 18-Bit Bus
Noise ( of Vdd)
of Shields
0.71V (55)
0 (a)
0.38V (29)
2 (b)
0.17V (13)
5 (c)
(a)
(b)
(c)
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Figure of Merit of Inductive Coupling

• Inductive coupling coefficient defined as
• A formula-based Keff model has been developed
• High fidelity between formula and noise voltage
  He-Xu, 2000

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Illustration of Keff Computation XuHe,2000
Keff(i,j) (f(i) g(j)) / 2 f(i) (Ni
gl)/(Nj gl) g(j) (gr Nj)/(gr-Ni)
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Inductance Minimization

• Staggered inverters/buffers
• Differential signals
• Nets with opposite switching signals can be
  placed adjacent to each other
• Decrease Lx noise at the cost of a higher Cx
  noise

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Mini-Summary

• Inductive crosstalk is globalized
• Inductive crosstalk affects both delay and signal
  integrity
• Inductive crosstalk is not sensitive to
• Spacing (and wire sizing)
• Net ordering
• Inductive crosstalk can be minimized by
• Shielding
• Buffering
• Ground plane
• Differential signal
• Signal termination

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Outline

• Capacitive noise
• Technology trends
• Capacitance model and characteristics
• Layout optimization
• Inductive noise and layout optimization
• When inductance become important
• Inductance model and characteristics
• Layout optimization
• Example SINO algorithm for both Cx and Lx noise
• Other noise sources

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SINO Problem He-Lepak, ISPD2KSimultaneous
Shield Insertion and Net Ordering

• Noise avoidance techniques
• Net ordering (track assignment / net placement)
• Shield insertion
• Shield is a wire directly connected to Vdd or Gnd

Vdd
Gnd
s4
G
s1
s3
s2
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SINO/NF Problem

• Given An initial placement P
• Find A new placement P via simultaneous shield
  insertion and net ordering such that
• P is capacitive noise free
• Sensitive nets are not adjacent to each other
• P is inductive noise free
• Sensitive nets do not share a block
• P has minimal area
• Equivalent to one-shield-one-signal
• When all nets are sensitive to one another

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SINO/NB Problem

• Given An initial placement P
• Find A new placement P via simultaneous shield
  insertion and net ordering such that
• P is capacitive noise free
• All nets in P have inductive noise less than a
  given value
• P has minimal area

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Properties of SINO Problems

• Theorem The optimal SINO/NF problem is NP-hard
• Theorem The optimal SINO/NB problem is NP-hard
• Theorem The maximum clique in the sensitivity
  graph is a lower bound on the number of blocks
  required for all SINO/NF solutions

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Sensitivity Graph for SINO Problem

• Graph indicating which nets are sensitive to
  one-another (verticesnets, edgesnets are
  sensitive)

One maximal clique
Sensitivity graph with clique size 3
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Greedy Shield Insertion

• Shield Insertion (SI)
• Insert shield when a Cx or Lx violation occurs
• Results depend strongly on the initial placement
• Net Ordering Shield Insertion (NOSI)
• First remove Cx coupling by net ordering, then
  perform shield insertion for Lx
• Results depend weakly on the initial placement

Separated NOSIsimultaneous algorithm works
better
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Graph Coloring SINO (GC)

• Our implementation Greedy-based GC
• Can solve with other GC methods as well
• Main contributions of SINO-GC
• Provide lower bound measurements for SINO/NF
• Comparative reference point

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Simulated Annealing SINO (SA)

• Cost Function is a weighted sum of
• Number of Cx violations
• Number of Lx violations
• Inductance Violation Figure (quantizes level of
  inductive noise)
• Area of Placement
• Random Moves
• Combine two random blocks in placement P
• Swap two (arbitrary) random s-wires in P
• Move a single random s-wire in P
• Insert a shield wire at a random location in P

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Quality of SINO/NB Solutions
Max. clique size in the sensitivity graph
SINO/NF SINO/NB SINO/NB SINO/NB SINO/NB
Kthresh Graph Coloring Greedy SI NOSI GC SA
Net Sensitivity Rate 10 Net Sensitivity Rate 10 Net Sensitivity Rate 10 Net Sensitivity Rate 10 Net Sensitivity Rate 10 Net Sensitivity Rate 10
1.0 3.2 (2.0) 5.0 2.8 2.0 1.8
2.0 3.2 (2.0) 4.2 1.2 2.0 1.0
Net Sensitivity Rate 30 Net Sensitivity Rate 30 Net Sensitivity Rate 30 Net Sensitivity Rate 30 Net Sensitivity Rate 30 Net Sensitivity Rate 30
1.0 6.0 (3.8) 13.2 4.4 4.2 3.0
2.0 6.0 (3.8) 13.2 2.8 3.8 2.0
Net Sensitivity Rate 60 Net Sensitivity Rate 60 Net Sensitivity Rate 60 Net Sensitivity Rate 60 Net Sensitivity Rate 60 Net Sensitivity Rate 60
1.0 13.6 (8.2) 22.4 5.4 8.2 5.0
2.0 13.6 (8.2) 22.4 4.0 8.2 3.4
of shields is fewer than lower bound for
SINO/NF CPU time is much less than existing net
ordering algorithms
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Expand to Full-Chip Level

• Shield estimation
• Crosstalk Modeling (LSK model) _at_ chip level
• Global routing synthesis
• Post-routing refinement with optimal crosstalk
  budgeting

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Shielding Estimation

• The number of shields for min-area SINO solution
  is
• Linear with number of nets (Nns)
• Quadratic with sensitivities (Si)
• Linear with crosstalk bounds (Kth,i)
• Holds for min-area SINO solutions
• Estimation can be used to guide routing synthesis

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Shielding Estimation

• For known crosstalk bound (Kth,i) but unknown
  sensitivity rate Si and unknown number of net
  Nns, the number of shields is
• To be used in global routing synthesis
• For known Si and Nns but unknown Kth,i
• To be used in noise budgeting

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Shielding Estimation (Contd)

• In most general case, the number of shields is

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Computation of LSK Value
Net i
Region H1
Region H2
Region H3

• For each sink, LSK value is
• Sum over the path from source to sink
• lj length of the region j where net i is routed
• Kij sum of inductive coupling coefficients for
  net i in region j

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Fidelity of LSK Model

• For SINO solutions, higher LSK values
• ? higher SPICE-computed noise using detailed RLC
  circuits

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Converting LSK Value to Noise Voltage

• Table building
• Consider SINO solution of parallel interconnect
  buses (i.e., two-pin nets)
• Compute and store both LSK values and noise
  voltages via SPICE simulation
• Table lookup (either two-pin or multi-pin nets)
• Linear interpolation and extrapolation

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Verification of LSK Model

• Errors less than 15 for SINO solutions to
  two-pin nets
• Errors less than 20 for SINO solutions to
  multi-pin nets

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GSINO Problem Formulation

• Given
• Pin locations of each net
• RLC crosstalk bound for each sink
• Decide
• Rectilinear Steiner tree for each net
• SINO solution within each routing region
• Such that
• RLC crosstalk constraint is satisfied for each
  sink
• Wire length is minimized
• Chip area is minimized

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Overall GSINO/LD Algorithm

• GSINO is NP-hard
• Sub-problem SINO is NP-hard
• High-quality solution via three-phase GSINO/LD
  algorithm
• Phase I Global routing with linear distribution
  of crosstalk bounds
• Phase II SINO within each region
• Developed in He-Lepak, ISPD00
• Phase III post-routing refinement (RF)

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Algorithm Phase I

• Routing topology generation
• L and Z shape routes within bounding box of all
  pins
• Leads to fixed path length from source to each
  sink
• Crosstalk bound distribution
• Linear distribution from source to each sink for
  fixed length
• More sophisticated solution presented later on

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Algorithm Phase I (Contd)

• Routing algorithm Iterative deletion (ID)
  Cong-Preas, Integration92
• Start with net connection graph (completed graph)
• Iteratively delete the edge with the largest
  weight
• Until graph becomes a tree

a f (wire_length) ß density (Ri) ?
overflow (Ri)

• Density signal nets estimated shields (via
  formula)
• Shielding area is reserved
• Shielding area is minimized as sensitive nets are
  automatically distributed to different regions
• Alternative global routing algorithm may be
  applied

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Algorithm Phase III

• Phase III post-SINO refinement (RF)
• Eliminate remaining but limited RLC noise
  violations
• Start with most severe crosstalk-violating net
• Decrease noise bound to allow one more shield in
  the least congested region using the formula
• Until no crosstalk violations
• Reduce routing congestion
• Start with most congested region
• Increase noise bound to remove one shield in the
  region using the formula
• Until new SINO solution without crosstalk
  violation

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Experiment Settings

• Comparison among
• IDNO
• ID ID-based global routing without considering
  shielding in the weight function
• NO net ordering to eliminate as much capacitive
  coupling as possible
• iSINO/LD ID SINO RF (best alternative)
• GSINO/LD
• ITRS 0.10um technology

Vdd 1.05V Load capacitance 60fF
Frequency 3GHz Wire width 1.0µm
Input rising time 33ps Wire thickness 1.1µm
Driver resistance 150O Wire spacing 0.8µm
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Benchmark Circuits
Number of nets Number of regions Number of pins Regions capacity Regions physical size (µm µm)
ibm01 13056 64 644096 45815 V12 H14 25 30
ibm02 19291 80 645120 79033 V22 H34 40 65
ibm03 26104 80 645120 80193 V20 H30 40 60
ibm04 31328 96 646144 94756 V20 H32 40 60
ibm05 29647 128 648192 127509 V42 H63 80 115
ibm06 34395 128 648192 125880 V20 H33 40 60

• Large scale industrial benchmark circuits
• Placement done by DRAGON Wang et al, ICCAD2K
• Uniform crosstalk constraints 0.15V (15 of Vdd)

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Number of Crosstalk-violating Nets
IDNO iSINO-RF iSINO-RF iSINO GSINO-RF GSINO
Sensitivity rate 30 Sensitivity rate 30 Sensitivity rate 30 Sensitivity rate 30 Sensitivity rate 30 Sensitivity rate 30
ibm01 1982 1982 177 0 79 0
ibm02 3370 3370 321 0 148 0
ibm03 5085 5085 365 0 196 0
ibm04 5392 5392 545 0 302 0
ibm05 4528 4528 552 0 209 0
ibm06 4951 4951 398 0 163 0
Sensitivity rate 50 Sensitivity rate 50 Sensitivity rate 50 Sensitivity rate 50 Sensitivity rate 50 Sensitivity rate 50
ibm01 2695 272 272 0 113 0
ibm02 4386 448 448 0 185 0
ibm03 6237 663 663 0 327 0
ibm04 6201 891 891 0 346 0
ibm05 7348 912 912 0 362 0
ibm06 6752 605 605 0 259 0

• Up to 25 of nets may have crosstalk violations
  in IDNO
• No crosstalk violations for iSINO and GSINO

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Expand to Full Chip

• Crosstalk Modeling
• Global routing synthesis
• Post-GR refinement with optimal crosstalk
  budgeting
• iSINO formulations
• iSINO/LP algorithm
• Experiment results
• Conclusions

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iSINO Formulation

• Given
• Global routing solution and crosstalk constraints
  at sinks
• Find
• A partition of crosstalk budget among routing
  regions and a SINO solution for each region
• Such that
• The crosstalk constraint is satisfied, and the
  routing area is minimized

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Overall Algorithm of iSINO

• Phase I noise budgeting for given global
  routing
• CB/1D, CB/2D, CB/2D-p
• Phase II SINO within each region
• Same as in GSINO
• Phase III post-routing refinement
• Same as in GSINO

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Crosstalk Budgeting for One-dimension Routing
(CB/1D Problem)

• Given
• One-dimension routing solution
• Find
• Partitioning of crosstalk bounds
• Such that
• The maximum height is minimized

Minimize hmax
source
sink
blockage
hmax
blockage
blockage
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CB/1D Problem formulation
source
sink
blockage
hmax
blockage
blockage
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Crosstalk Budgeting for Pseudo Two-Dimension
Routing (CB/2D-p problem)

• Given
• two-dimension routing solution
• Find
• partition crosstalk bounds among all routing
  regions
• Such that
• the weighted sum of maximum height and width is
  minimized.

Minimize ?wmax ?hmax
sink i1
blockage
source j
sink j1
blockage
source i
hmax
blockage
blockage
sink i2
sink j1
wmax
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CB/2D-p problem formulation
sink i1
blockage
source j
sink j1
blockage
source i
hmax
blockage
blockage
sink i2
sink j1
wmax
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Crosstalk Budgeting for Two-Dimension Routing
(CB/2D problem)

• Given
• two-dimension routing solution
• Find
• partition crosstalk bounds among all routing
  regions
• Such that
• the total chip area is minimized.

Minimize wmax hmax
sink i1
blockage
source j
sink j1
blockage
source i
hmax
blockage
blockage
sink i2
sink j1
wmax
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CB/2D problem formulation
sink i1
blockage
source j
sink j1
blockage
source i
hmax
blockage
blockage
sink i2
sink j1
wmax
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Main Theorem

• CB/1D and CB/2D-p problem are linear programming
  (LP) problem
• all constraints and the objective are linear
• CB/2D problem are non-linear programming (NLP)
  problem
• The objective is nonlinear (but all constraints
  are linear though)

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Conclusions and Further Study

• LP-based noise budgeting reduce routing area by
  5.71
• Details see reading assignment
• Multi-level routing may be used to reduce runtime
  of iterative deletion and consider integrity for
  both power and signal nets
• Student presentation
• Detailed modeling for capacitive noise
• Bottom-up model
• 2-? model