EE%20201A%20Noise%20Modeling

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EE 201ANoise Modeling

• Jeff Wong and Dan Vasquez
• Electrical Engineering Department
• University of California, Los Angeles

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Efficient Coupled Noise Estimation for On-Chip
Interconnects

• Anirudh Devgan
• Austin Research Laboratory
• IBM Research Division, Austin TX

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Motivation

• Noise failure can be more severe than timing
  failure
• Difficult to control from chip terminals
• Expensive to correct (refabrication)
• Circuit or timing simulation (like SPICE) can be
  used
• Linear reduction techniques can be applied for
  linearly modeled circuits
• i.e. moment matching methods
• Inefficient for noise verification and avoidance
  applications

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Noise Estimation

• The paper presents an electrical metric for
  efficiently estimating coupled noise for on-chip
  interconnects
• Capacitive coupling between an aggressor net and
  a victim net leads to coupled noise
• Aggressor net switches states source of noise
  for victim net
• Victim net maintains present state affected by
  coupled noise from aggressor net

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Circuit Schematic

• Lets analyze the case for one aggressor net and
  one victim net

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Circuit Equations

• Coupled equation for circuit
• In Laplace domain

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Circuit Equations

• Aggressor net
• Victim net

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Transfer Function

• Transfer function
• Simplifications (details later)
• Simplified transfer function

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Simplifications

• A12 0
• No resistive (or DC) path exists from the
  aggressor net to the victim net
• A21 0
• No resistive (or DC) path exists from the victim
  net to the aggressor net
• B2 0
• No resistive (or DC) path exists from the
  voltage/noise source to the victim net

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Maximum Induced Noise

• H(s0) 0
• Coupling between aggressor and victim net is
  purely capacitive
• Maximum induced noise can be computed
• Assume Vs is a finite or infinite ramp

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Maximum Induced Noise

• Final value theorem
• Ramp input u(s)

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Circuit Interpretation
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Circuit Computations(matrix method)

• Step 1 Compute
• Requires circuit analysis of the aggressor net
• Step 2 Compute
• Requires a matrix multiplication
• Step 3 Compute
• Requires circuit analysis of the victim net

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Circuit Computations(by inspection)

• Step 1 Compute
• Aggressor circuit transformation
• Replace input source with its derivative
• Replace aggressor nets capacitors with open
  circuits

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Circuit Computations (by inspection)

• Step 1 Compute
• Typical interconnects
• Negligible loss no resistive path to ground

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Circuit Computations (by inspection)

• Step 2 Compute
• Convert steady state derivative on the aggressor
  net to a current on the victim net
• i index of node on the victim net
• j index of node on the aggressor net

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Circuit Computations (by inspection)

• Step 3 Compute
• Victim circuit transformation
• Replace capacitors with coupling currents
• The voltage at each node corresponds to that
  nodes maximum induced noise

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Circuit Computations (by inspection)

• Step 3 Compute
• Typical interconnects
• Compute by inspection in linear time

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Circuit Computations (by inspection)

• Step 3 Compute
• 3RC Circuit example

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Computation Costs

• Step 1
• No computation required
• Step 2
• Simple multiplications
• Step 3
• Simple multiplications
• Multiple aggressor nets
• Coupling currents from step 2 determined from a
  linear superposition

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Experiment

• Typical small RC interconnect structure
• Rise time of 200 ps or 100 ps
• Power supply voltage of 1.8 V
• Conventional circuit simulation vs. proposed
  metric
• Run-time comparisons for various circuit sizes

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Accuracy Results

• 10 nodes, 200 ps rise time

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Accuracy Results

• 10 nodes, 100 ps rise time

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Accuracy Results

• Metric accuracy degrades with reduction in rise
  times
• Metric estimation is more conservative than
  circuit models
• Fast rise times dont allow circuit to reach ramp
  steady state noise
• Loading of interconnect normally does not allow
  for very small rise times
• Metric accuracy should be acceptable for many
  applications

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Run-time Results

• Arnoldi-based model reduction used a matrix
  solution to compute circuit response
• Requires repeated factorizations, eigenvalue
  calculations, and time exponential evaluations

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Conclusions

• The proposed metric determines an upper bound on
  coupled noise for RC and over-damped RLC
  interconnects
• Metric becomes less accurate as rise time
  decreases
• The proposed metric is much more run-time
  efficient than circuit modeling methods

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Improved Crosstalk Modeling for Noise Constrained
Interconnect Optimization

• Jason Cong, David Zhigang Pan Prasanna V.
  Srinivas
• Department of Computer Science, UCLA
• Magma Design Automation, Inc.
• 2 Results Way, Cupertino, CA 95014

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Motivation

• Deep sub-micron net designs have higher aspect
  ratio (h/w)
• Increased coupling capacitance between nets
• Longer propagation delay
• Increased logic errors --- Noise
• Reduced noise margins
• Lower supply voltages
• Dynamic Logic
• Crosstalk cannot be ignored

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Aggressor / Victim Network

• Assuming idle victim net
• Ls Interconnect length before coupling
• Lc Interconnect length of coupling
• Le Interconnect length after coupling
• Aggressor has clock slew tr

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2-? Model

• Victim net is modeled as 2 ?-RC circuits
• Rd Victim drive resistance
• Cx is assumed to be in middle of Lc

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2-? Model Parameters
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Analytical Solution
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Analytical Solution part 2

• s-domain output voltage
• Transform function H(s)

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Analytical Solution part 3

• Aggressor input signal
• Output voltage

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Simplification of Closed Form Solution

• Closed form solution complicated
• Non-intuitive
• Noise peak amplitude, noise width?
• Dominant-pole simplification

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Dominant-Pole Simplification
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Intuition of Dominant Pole Simplification

• vout rises until tr and decays after
• vmax evaluated at tr

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Extension to RC Trees

• Similar to previous model with addition of lumped
  capacitances

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Results

• Average errors of 4
• 95 of nets have errors less than 10

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Spice Comparison

• peak noise noise width

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Effect of Aggressor Location

• As aggressor is moved close to receiver, peak
  noise is increased

Ls varies from 0 to 1mm Lc has length of 1mm Le
varies from 1mm to 0
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Optimization Rules

• Rule 1
• If RsC1 lt ReCL
• Sizing up victim driver will reduce peak noise
• If RsC1 gt ReCL and tr ltlt tv
• Driver sizing will not reduce peak noise
• Rule 2
• Noise-sensitive victims should avoid
  near-receiver coupling

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Optimization Rules part 2

• Rule 3
• Preferred position for shield insertion is near a
  noise sensitive receiver
• Rule 4
• Wire spacing is an effective way to reduce noise
• Rule 5
• Noise amplitude-width product has lower bound
• And upper bound

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Conclusions

• 2-? model achieves results within 6 error of
  HSPICE simulation
• Dominant node simplification gives intuition to
  important parameters
• Design rules established to reduce noise

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References

• Anirudh Devgan, Efficient Coupled Noise
  Estimation for On-chip Interconnects, ICCAD,
  1997.
• J. Cong, Z. Pan and P. V. Srinivas, Improved
  Crosstalk Modeling for Noise Constrained
  Interconnect Optimization, Proc. Asia South
  Pacific Design Automation Conference (ASPDAC),
  Jan. 30 - Feb. 2, 2001, Pacifico Yokohama, Japan.