Trigger System Functions

1
Trigger System Functions

• Master/Slave Operation
• Located in Readout Boards BE-FPGA, but only
  active as Master in one slot.
• Master controls asynchronous Trigger
  feed-through.
• Trigger fanned-out to other Readout Boards via
  backplane pins and custom connections.
• Receives Trigger again as Slave.
• VME Interface
• Trigger system controlled via VME
  registers/memory.
• Digitiser Stores incoming signals prior to
  trigger
• Allows pre-trigger environment to be stored
  with event data.
• Veto Logic
• Inhibits Triggers while busy, protects against
  double-triggers.

2
Trigger System Functions (Continued)

• Interfaces to other slots and external devices
• May have back-of-crate card to provide fan-out
  connector.
• Some signals can generate interrupts
  (BeamOn/Off).
• Able to delay outgoing external Triggers (5ns
  steps).
• Stand-alone functions
• Periodic/Random Trigger, Clock generator.
• Sequencer/Sink - Play/Record (pre-)trigger
  events
• 16kBytes (clock periods) deep - pending FPGA
  utilisation.
• Good for repeatability and fast trigger testing
  (sync. only).
• Sink stores outgoing signals - provides software
  testability.

3
Trigger System Functional Diagram
J2 EXT NIM 16 In
J2 BP LVDS 8 Out EXT NIM 16 Out
Edge Detect
Internal Trig Osc Randomiser
IRQ
VME
START
SEQ
1x BeamOn
Beam On Sync Enable
IRQ
STOP
VME
8x Trigger
VME
4x PreTrigger
VME
SEQ
Pre-Trigger Sync Enables
Trigger Gate Generate
Trigger Latch,Veto
Trigger Sync
4x SR
VME
4x Trigger
VME
IRQ
SEQ
SINK
4x Activity
Activity Sync Enables
VME
START
Width/Delay
STOP
Delayed Trig 1
8 x Counter Delays
4x SR
VME
VME
SINK
Delayed Trig 8
160MHz
VME
SINK
SEQ
VME
1x Veto
Veto Sync Enable
SR
VME
6x Spare
4x Spare
Sequencer Sink 16KByte RAM
Digitiser 32bit Shift Registers (x9)
Clock Control
J0 LVDS 5 In
J0 LVDS 2 Out
1x Clock
1x Clock
40MHz
1x Trigger
VME
1x Spare
3x Spare
BE FPGA - Trigger System
(v4 - 22/9/2003)
4
Trigger/Event Data Integration
FE-BE Control Transfer
Front-End Data
Trig
Trigger Processor
Pre-Triggers
Readout Data Block Select Build
Backplane Data Transfer
5
Trigger Status
External Interface Mostly specified. Requires
back-of-crate cable/board system
finalised. Trigger Processing System Outline
complete. Requirements understood. Overall code
structure in place, but nuts-and-bolts not
coded. More work required on asynchronous trigger
transfer skew. Simulation of not
started. Integration with existing firmware
Started. Able to edit existing FED design in HDL
Designer. Register Read/Write path
understood. Coupling to event data block header
not understood.