Designing Sequential Logic Circuits

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Designing SequentialLogic Circuits
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
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Sequential Logic
2 storage mechanisms positive feedback
charge-based
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Naming Conventions

• In the text
• a latch is level sensitive
• a register is edge-triggered
• Many different naming conventions
• flip-flops (level or edge?)
• Transparency?
• Dual edge/level

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Latch versus Register

• Register- stores if clock rises, never
  transparent (mostly)

• Latch- stores if clock is low transparent if
  clock is high

D
Q
D
Q
Clk
Clk
Clk
Clk
D
D
Q
Q
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Latch-Based Design

• N latch is transparentwhen f 0

• P latch is transparent when f 1

f
N
P
Logic
Latch
Latch
Logic
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Timing Definitions
CLK
Register
t
D
Q
t
t
hold
setup
D
DATA
CLK
STABLE
t
t
c
lk2q
Q
DATA
STABLE
t
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Maximum Clock Frequency
f
Timing Constraints tclk2q tp(comb) tsetup
T tcdreg tcdlogic gt thold First Constraint
ensures clock is slow enough that Registers
sample correct value Second Constraint ensures
that there is no path after the clock changes to
alter the previously stored data
Register
LOGIC
t
P(comb)
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Positive Feedback Bi-Stability
1
1
o
o
V
V
5
2
i
V
A,B Stable points C is unstable(metastable) Feedb
ack moves state to Stable points, eventually
1
o
V
5
2
i
V
V
V
V

V
V

V
i
1
o
2
o
2
i
1
o
1
i
2
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Writing a Static Latch
Use the clock to distinguish between the
transparent and opaque states
Forcing the state (can implement as NMOS-only)
Converting into a MUX
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Mux-Based Latches
Negative latch (transparent when CLK 0)
Positive latch (transparent when CLK 1)
CLK
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Master-Slave Register
CLK
D
Qm
Qm
Q
D
Q
CLK
CLK
Two opposite latches trigger on edge Also called
master-slave latch pair
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Clk-Q Delay
Clock to Q delays are Different for rising and
falling Transitions Use Worst Case not Avg!
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Setup Time (MS register)
Q
Qm
D
Q
D
Qm
CLK
Setup 0.20nS Failed to pass D
Setup 0.21nS Passed D
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Cross-Coupled Pairs
NOR-based set-reset
Q Q 0 1 -
Q Q 1 0 -
R 0 0 1 1
S 0 1 0 1
S
Q
R
Q
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Cross-Coupled NAND
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Sizing Issues
2
W0.5
1
Q (V)
W0.7
W0.8
2.5
3.5
3.0
1
0
2
W1
W/L (M5,M6) M26
Output voltage dependence on transistor width
Transient response
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Storage Mechanisms
Dynamic (charge-based)
Static
CLK
D
Q
CLK
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Making a Dynamic Latch Pseudo-Static
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Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
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Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
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Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
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Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
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Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
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Setup/Hold Time Illustrations
Hold-1 case
0
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Setup/Hold Time Illustrations
Hold-1 case
0
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Setup/Hold Time Illustrations
Hold-1 case
0
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Setup/Hold Time Illustrations
Hold-1 case
0
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Setup/Hold Time Illustrations
Hold-1 case
0
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Other Latches/Registers C2MOS
Keepers can be added to make circuit
pseudo-static
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Insensitive to Clock-Overlap
V
V
V
V
DD
DD
DD
DD
M
M
M
M
2
6
2
6
M
0
0
M
4
8
X
X
D
Q
D
Q
M
1
M
1
3
7
M
M
M
M
1
5
1
5
(a) (0-0) overlap
(b) (1-1) overlap
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Pipelining
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Other Latches/Registers TSPC
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Pulse-Triggered LatchesAn Alternative Approach
Ways to design an edge-triggered sequential cell
Master-Slave Latches
Pulse-Triggered Latch
L1
L2
L
Data
Data
D
Q
D
Q
D
Q
Clk
Clk
Clk
Clk
Clk
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Latch-Based Pipeline
CLK
CLK
CLK
F
G
F
G
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Non-Bistable Sequential Circuits-Schmitt Trigger

• VTC with hysteresis
• Restores signal slopes

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Noise Suppression Schmitt Trigger
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CMOS Schmitt Trigger
Moves switching threshold of the first inverter
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Schmitt Trigger Simulated VTC
2.5
2.5
2.0
2.0
V
1.5
1.5
M
1
(V)
(V)
x
X
V
1.0
1.0
V
V
M
2
k
1
k
3
k
2
0.5
0.5
k
4
0.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
V
(V)
V
(V)
in
in
Voltage-transfer characteristics with hysteresis.
The effect of varying the ratio of the
PMOS device
M
. The width is
k
0.5 m.
m
4
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CMOS Schmitt Trigger (2)
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Multivibrator Circuits
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Transition-Triggered Monostable
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Monostable Trigger (RC-based)
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Astable Multivibrators (Oscillators)
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Relaxation Oscillator
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Voltage Controller Oscillator (VCO)
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Differential Delay Element and VCO
two stage VCO
simulated waveforms of 2-stage VCO
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Homework 7

1. A common way to characterize registers is to
   measure the timing aperture which is the total
   window in which transitions on data are not
   correctly output. This is done by making two
   clocks which are close, but not the same so that
   the relative phase drifts slowly with each cycle.
   Construct a pseudo-static master/slave flip-flop
   in SUE with the assumption that the input is
   driven by a unit inverter (2/1, min width nmos),
   the clock is driven by a 2x inverter. Optimize
   your designs to minimize the timing aperture
   (setuphold) and clock to Q assuming the output
   load is 2 min inverters. Simulate your designs in
   SPICE and turn in both the designs (annotated
   schematics and spice results plz. dont waste
   paper!)
2. Do problem 1 again, with TSPC based flipflop.
   (High performance)