Noise Analysis of PowerPC

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Noise Analysis of PowerPC Circuits Implemented
with FinFET Devices Based on IBM Device
Technology and Pspice MacroModeling Techniques
Peter Chan Academic Advisor Prof. J.
Hedrick Industrial Advisors (IBM) E. Hedberg,
N. Rohrer
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Presentation Outline

1. Motivations Behind the Project
2. Brief Overview of FinFET and SOI Devices
3. Project Activities at IBM Burlington
   (Microelectronics Division)
4. Project Activities at Union College
5. Acknowledgements and Reflections

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Motivations Behind the Project

• Work on Project with Industrial Significance

2. Development of FinFET Devices for Future
Commercial Use
3. Performance Comparison of SOI
(Silicon-On-Insulator) and FinFET Devices

• 4. Noise Problems in Recent PowerPC Projects

5. Gain a Better Understanding of the
Functionality of a FinFET Device
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Brief Overview of SOI and FinFET Devices
SOI Devices

• Operation - Based on the History of Charge

• Performance - Less Junction Capacitance,
• Elimination of Bulk Effect

• Structure - Similar to Conventional FET
• (Main Variation Implanting 02 to Create Oxide)

FinFET Devices

• Operation - Similar to Conventional FET But
• With Two Gates Instead of One

• Performance Better Current Density, Faster
• Switching

• Structure - Three Dimensional Require New
• Fabrication Process

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Project Activities at IBM Burlington - I
1. Integration of FinFET Models into Cadence
Platform at PowerPC
2. Noise Simulation of PowerPC Circuits Dynamic
Logic NAND Circuit, Latch Circuit And SRAM Cell
3. Creation of Customized Noise Analysis Tests
for Each Circuit
Insert Noise Signals of Varying Height and Width
at the Circuit Input
Height Variation (Voltage) 0 to 1.15 Volts
In Increments of 0.05 Volts
Width Variation (Voltage) 4 picoseconds to 18
picoseconds In Increments of 2 picoseconds
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Project Activities at IBM Burlington - II
3. (Continued)
Example of a Noise Analysis Test
Noise Performance Concerns
-10 Drope Tolerance
-Hard Failures
4. Generate mass simulation results for noise
analysis in a feasible and convenient
manner
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Project Activities at IBM Burlington - III
5. Observation from Noise Analysis Results
FinFET Devices Has Less Noise Tolerance Than SOI
Devices
Why?
Hard to Verify Due to Lack of Direct Access to
Device Models
How much more noise in FinFET than SOI device?
Dynamic NAND Circuit 23.5 , Latch Circuit
37.9, SRAM Cell 21.9
Impact of these Results
-Layout of Circuits on Chip
-Parameters of the Devices
-Provide a Better Sense of the Noise Performance
of FinFET Devices Implemented in ULSI
Applications
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Project Activities at Union College - I
1. Create Pspice Netlist for PowerPC Circuits
2. Implement Macromodel Techniques for Model of
FinFET Device Designing a System to Create a
Simulated Device
-Two Main Types of Circuits
I. Circuit to Implement Equations-e.g. Saturated
Current, Capacitance Between Drain and Gate in
Linear Mode
Main Components Linear and Non-Linear
Voltage/Current Controlled Devices
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Project Activities at Union College - II
2. (Continued)
II. Circuit to Control the Behavior of Device-e.g
Mode of the Transistor (Saturated, Linear or
Cutoff)
3. Create Software Programs to Run Noise
Simulations of MacroModel -Based FinFET Device

• Create New Netlist with Device Parameter Values
• (e.g. Cox, Width) from User

-Run Batch Noise Simulations
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Acknowledgements and Reflections

• Reflections
• 1. Better Understanding Between Industrial and
  Academic Environments
• 2. Developing Solutions to Unknown Problems

Acknowledgements 1. IBM (Especially the PowerPC
Group) 2. Professor J. Hedrick 3. Union
College ECE Department