BWRC RF Analog: Circuits and Automated Design

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BWRC RF AnalogCircuits and Automated Design

• Fernando De Bernardinis, Brian Limketkai, Patrick
  McElwee, Johan Vanderhagen,
• Andrei Vladimirescu, Bob Brodersen

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Overview

• Project Goals
• Desired Flow
• Present Attempts
• Enabling Research
• Conclusions

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Goals

• Low-power analog CMOS circuits for RF
• Develop continuous design flow from system-level
  abstraction to chip implementation
• Automatic porting to new technologies
• Order-of-magnitude time reduction from system
  spec to tested chip
• Provide high-level visualization of design space
  trade-offs
• Generate sized design through automatic
  optimization from block-level diagram

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Constraints

• Use best-in-class commercial CAE tools
• Provide integration for optimal top-down design
• Align with standard foundry design flow
• source for process parameters
• Re-use existing designs
• Challenge
• best tools in flow from different EDA suppliers

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Infrastructure Requirements

• Submicron MOSFET model equations
• continuous over all regions of operation
• Analytical formulation of performance functions
  of analog blocks
• expressed as a function of key design variables
• Above appropriate for analytical optimization
• Performance space representation of captured
  designs
• for design space exploration
• Physical connection to schematic

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Desired Flow

• Generate architecture/block-diagram from
  specification
• Optimize key design variables for modules in
  block diagram
• Verify sized circuit schematics to behavioral
  description
• Simulation-based Optimization of remaining W/Ls
  to match specification
• Transfer (automatic) sized schematic to layout

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BWRC Design Methodology
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BWRC Automated Analog Design Flow
System eval
System spec
Architecture
Simulation
Feasibility
Verification
Analysis
Design
Generate
Optimization
circuit
circuit
layout
schematics
behavior
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Levels of Representation to Design Tools

• Functional simulation/optimization
• Framework (C, Matlab) for
• Performance evaluation block diagram
• Optimization to Spec constraints power,
  gain,BW, NF,...
• SPICE-level simulation/verification/model develop
• Behavioral model (Verilog/VHDL AMS, MAST, C)
• for top-level circuit model refinement against
  schematic
• design debugging of complete circuit
• Transistor-level, detailed circuit
• Combine descriptions for optimal thruput/accuracy
• Electrical to Physical (Layout)

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Design Continuum over Tools

• Levels of representations
• Matlab
• Simulink
• Verilog-A
• Xtor Schematic
• Layout

Same Simulator
Same Parameters
Same Simulator
Same Parameters
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BWRC Automated Analog Design Flow Feasibility
System eval
System spec
Architecture
Simulation
Feasibility
Verification
Analysis
Design
Generate
Optimization
circuit
circuit
layout
schematics
behavior
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System-level Exploration

• System level design exploration is based on
  well-defined set of circuit models
• at several levels of abstraction
• Feasibility of a set of design constraints is
  difficult without building the block
• In the digital world, cost is more an issue than
  feasibility
• Significant improvements are often due to
  architectural solutions
• importance of top-level exploration
• Cannot fully automate this, analog design is
  still art

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System-level Exploration Proposed

• Proposed approach
• establish a bottom-up link between abstract block
  models and real implementations
• Characterize the performance achievable by
  individual circuit topologies
• Establish a mapping function to represent a
  circuit
• F(input params, output params) 1
• In a top-down flow, we are mostly interested in
  the output space
• G(Power, Gain, NF, IIP3, P-1dB, ) 1
• Use simulations to sample F and G
• Computationally expensive, but offline (library
  characterization)

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System-level Exploration An Example
Input Params W1, W2, W3, W4, L3, L4, Ibias

• Example
• Original, R7? R7
• Shown, projection in R3

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System-level Exploration

• 2-D projections of a 4-D relation G

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BWRC Automated Analog Design Flow
Design/Optimize
System eval
System spec
Architecture
Simulation
Feasibility
Verification
Analysis
Design
Generate
Optimization
circuit
circuit
layout
schematics
behavior
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Circuit Design and Optimization

• Performance Equations
• based on MOSFET equations
• capture relation between design constraints and
  transistor sizes
• in C or Matlab
• hierarchical
• Optimization
• Objective Minimize power
• Constraints Gain, NF, IIP3, P-1dB

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MOSFET Model Requirements

• Simple and physical
• Single expression for the three regions of
  interest
• weak, moderate and strong inversion
• Circuit-design-oriented parameters
• Formulation with optimization in mind

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MOSFET gm/ID
Charge-sheet Model based on surface potential
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MOSFET Charge Characterization
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MOSFET fT

• The Bad News!

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MOSFET Design Parameters

• Ultimate goal
• Minimize Power
• Gain/BW/Noise compromises
• Keyed on inversion level selection for each
  block/transistor
• Results
• I and W, L of transistors

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Levels of Representation

• Choice of detail at each level critical for
• design performance
• design cycle
• simulation time
• iterations
• Example Pipelined ADC

2 GHz
Mobile Receiver
ADC
I
LNA
Q
ADC
PLL
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Hierarchical Circuit Model Pipelined ADC

• 10-bit A/D -gt 9 stages
• Objective
• Min P SIOTA
• Global Constraints
• Noise
• Nonlinearity
• Additional Constraints
• tsettle, gm, f

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Pipelined ADC Stage

• Unknowns
• 8N1 -gt 73
• VPP, (CS,CF), CL, f, Gm, I
• Constraints
• 173
• Results
• I, W, C

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BWRC Automated Analog Design Flow Verification
System eval
System spec
Architecture
Simulation
Feasibility
Verification
Analysis
Design
Generate
Optimization
circuit
circuit
layout
schematics
behavior
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Design Verification

• Architecture selected and circuit blocks key
  parameters optimized
• Complete flat circuit diagram is generated
• Spice verification against specification
• Secondary design improvements by numerical
  optimization

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Simulator Choices

• Spectre
• RF analysis, Verilog-A, MOS Models, SP WS
• - Poor optimization, cumbersome setup
• ADS
• RF analysis, optimization, Simulink tie-in
• ? Robustness of Spice, MOS models
• HSPICE
• Optimization setup, Model support
• - No behavioral, RF

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BWRC Automated Analog Design Flow Layout
System eval
System spec
Architecture
Simulation
Feasibility
Verification
Analysis
Design
Generate
Optimization
circuit
circuit
layout
schematics
behavior
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Layout Generation
Need functionality to go directly from schematic
to layout.
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Hierarchical P-Cell Layout

• Analog Layout Building Blocks
• Common Centroided
• Transistors
• (e.g. 2 centroided 6 finger
• PMOS transistors)
• Cascoded
• Transistors
• (e.g. small PMOS cascode
• device with larger current
• mirror device)

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Hierarchical P-Cell Layout (cont.)

• Multi-Fingered
• Transistors
• (e.g. 5 finger high-speed
• PMOS transistor)
• Replicated Unit Cell
• Passive Devices
• (e.g. 4 unit cell MIM
• capacitors)

Use these building blocks to create parameterized
layouts for schematic.
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Other Layout Options

• Issuess with P-Cell Layouts
• Scalability
• Robustness?
• Options
• Virtuoso XL
• Older versions do not provide reliable routing
  for analog blocks.
• Newer versions need to be evaluated.
• Neolinears NeoCell
• Cadence will be distributing and supporting
  NeoCell.
• Also needs to be evaluated.

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Conclusion

• Goal low-power analog circuits for RF
• Automated design system based on known circuit
  topologies
• needs
• characterization and model development to set up
• simulation/verification and schematic-to-layout
  support
• Radio Chip in a Day?
• Yes, but
• design constraints must be met with characterized
  cells
• back-end tools must deliver!