ECT 358

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ECT 358

• Lecture 8
• Adder Design

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Its good to be a Christian and know it, but its
better to be a Christian and show it.

• By this shall all men know that ye are my
  disciples, if ye have love one to another.
• John 1335

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Full Adder Sample Design

• Consider adding two four-bit numbers, say 0101
  and 1001
• Looking at the example problem, we can build the
  following truth table for a single stage of the
  adder

Input Input Input Output Output
a b carry-in sum carry-out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
0101 1001 1110
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Full Adder Equations

• Using the minterm approach
• Sum abcin abcin abcin abcin
• Carry-out abcin abcin abcin abcin

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Verilog HDL for Full Adder Module

• //fulladder.v
• //Full Adder Module using minterm equations
• module fulladder(a,b,cin, sum, cout)
• input a, b, cin
• output sum, cout
• assign sum !a !b cin !a b !cin
  a !b !cin a b cin
• assign cout !a b cin a !b cin
  a b !cin a b cin
• endmodule

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Behavioral Code Concept

• Previous example provides structural HDL which is
  one-to-one with the logic
• Can also specify the module by specifying its
  behavior

//fulladder_b module fulladder_b(a, b, cin,
sum, cout) input a, b, cin output sum,
cout assign cout, sum a b cin
//behavioral assignment endmodule
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A Two-bit Ripple Carry Adder

• If we treat the Full Adder Module as a black box,
  we can use it to make multiple bit adders

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Verilog HDL for Two-bit Ripple Carry Adder

• //add_2_r.v
• //Two-bit ripple carry adder example
• //Uses fulladder module
• module add_2_r(A, B, cin, SUM, cout1)
• input 10 A,B
• input cin
• output 10 SUM
• output cout1
• wire 10 A, B, SUM
• wire cin, cout1
• fulladder FA1(A1, B1, cout0, SUM1, cout1)
• fulladder FA0(A0, B0, cin, SUM0, cout0)
• endmodule

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Design Entry Example (Cont) Four-bit slice,
ripple carry adder module

• //add_4_rc.v
• //Four-bit ripple carry adder example
• //Uses fulladder.v module
• module add_4_rc(A, B, cin, SUM, cout)
• input 30 A,B
• input cin
• output 30 SUM
• output cout
• wire c0,c1,c2
• fulladder FA3(A3, B3, c2, SUM3, cout)
• fulladder FA2(A2, B2, c1, SUM2, c2)
• fulladder FA1(A1, B1, c0, SUM1, c1)
• fulladder FA0(A0, B0, cin, SUM0, c0)
• endmodule

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Design Entry Example (Cont) 16 Bit Adder

• //add_16_behavioral.v
• module add_16_behavioral (A, B, cin, SUM, cout)
• input 150 A,B
• input cin
• output 150 SUM
• output cout
• assign cout, SUM A B cin
• endmodule