EEL 4768 Computer System Design 2

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EEL 4768Computer System Design 2

• Lecture 6 Designing a Single Cycle Datapath

2
How to Design a Processor step-by-step

• 1. Analyze instruction set gt datapath
  requirements
• the meaning of each instruction is given by the
  register transfers
• datapath must include storage element for ISA
  registers
• possibly more
• datapath must support each register transfer
• 2. Select set of datapath components and
  establish clocking methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that affects
  the register transfer.
• 5. Assemble the control logic

3
The MIPS Instruction Formats

• All MIPS instructions are 32 bits long. The
  three instruction formats
• R-type
• I-type
• J-type
• The different fields are
• op operation of the instruction
• rs, rt, rd the source and destination register
  specifiers
• shamt shift amount
• funct selects the variant of the operation in
  the op field
• address / immediate address offset or immediate
  value
• target address target address of the jump
  instruction

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Step 1a The MIPS-lite Subset for today

• ADD and SUB
• addU rd, rs, rt
• subU rd, rs, rt
• OR Immediate
• ori rt, rs, imm16
• LOAD and STORE Word
• lw rt, rs, imm16
• sw rt, rs, imm16
• BRANCH
• beq rs, rt, imm16

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Logical Register Transfers

• RTL gives the meaning of the instructions
• All start by fetching the instruction

op rs rt rd shamt funct MEM PC op
rs rt Imm16 MEM PC
inst Register Transfers ADDU Rrd lt Rrs
Rrt PC lt PC 4 SUBU Rrd lt Rrs
Rrt PC lt PC 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 LOAD Rrt lt MEM
Rrs sign_ext(Imm16) PC lt PC 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrt PC lt PC
4 BEQ if ( Rrs
Rrt ) then PC lt PC sign_ext(Imm16)
00
else PC lt PC 4
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Step 1 Requirements of the Instruction Set

• Memory
• instruction data
• Registers (32 x 32)
• read RS
• read RT
• Write RT or RD
• PC
• Add and Sub register or extended immediate
• Add 4 or extended immediate to PC

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Step 2 Components of the Datapath

• Combinational Elements
• Storage Elements
• Clocking methodology

8
Combinational Logic Elements (Basic Building
Blocks)
CarryIn

• Adder
• MUX
• ALU

A
32
Sum
Adder
32
B
Carry
32
Select
A
32
Y
MUX
32
B
32
OP
A
32
Result
ALU
32
B
32
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Storage Element Register (Basic Building Block)

• Register
• Similar to the D Flip Flop except
• N-bit input and output
• Write Enable input
• Write Enable
• negated (0) Data Out will not change
• asserted (1) Data Out will become Data In

Write Enable
Data In
Data Out
N
N
Clk
10
Storage Element Register File
RW
RA
RB

• Register File consists of 32 registers
• Two 32-bit output busses
• busA and busB
• One 32-bit input bus busW
• Register is selected by
• RA (number) selects the register to put on busA
  (data)
• RB (number) selects the register to put on busB
  (data)
• RW (number) selects the register to be
  writtenvia busW (data) when Write Enable is 1
• Clock input (CLK)
• The CLK input is a factor ONLY during write
  operation
• During read operation, behaves as a combinational
  logic block
• RA or RB valid gt busA or busB valid after
  access time.

Write Enable
5
5
5
busA
busW
32
32 32-bit Registers
32
busB
Clk
32
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Storage Element Idealized Memory
Write Enable
Address

• Memory (idealized)
• One input bus Data In
• One output bus Data Out
• Memory word is selected by
• Address selects the word to put on Data Out
• Write Enable 1 address selects the memoryword
  to be written via the Data In bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write
  operation
• During read operation, behaves as a
  combinational logic block
• Address valid gt Data Out valid after access
  time.

Data In
DataOut
32
32
Clk
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Clocking Methodology
Clk
Setup
Hold
Setup
Hold
Dont Care

• All storage elements are clocked by the same
  clock edge
• Cycle Time CLK-to-Q Longest Delay Path
  Setup Clock Skew
• (CLK-to-Q Shortest Delay Path - Clock Skew) gt
  Hold Time

13
Step 3

• Register Transfer Requirements gt Datapath
  Assembly
• Instruction Fetch
• Read Operands and Execute Operation

14
3a Overview of the Instruction Fetch Unit

• The common RTL operations
• Fetch the Instruction memPC
• Update the program counter
• Sequential Code PC lt- PC 4
• Branch and Jump PC lt- something else

Instruction Word
32
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3b Add Subtract

• Rrd lt- Rrs op Rrt Example addU rd,
  rs, rt
• Ra, Rb, and Rw come from instructions rs, rt,
  and rd fields
• ALUctr and RegWr control logic after decoding
  the instruction

Rs
Rt
Rd
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
Clk
busB
32
16
Register-Register Timing
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memory Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
RegWr
Old Value
New Value
Register File Access Time
busA, B
Old Value
New Value
ALU Delay
busW
Old Value
New Value
Rs
Rt
Rd
ALUctr
Register Write Occurs Here
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
Clk
busB
32
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3c Logical Operations with Immediate

• Rrt lt- Rrs op ZeroExtimm16

Rt
Rd
RegDst
Mux
Rs
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
Result
32
32 32-bit Registers
ALU
32
32
Clk
busB
32
Mux
ZeroExt
imm16
32
16
ALUSrc
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3d Load Operations

• Rrt lt- MemRrs SignExtimm16 Example lw
  rt, rs, imm16

Rt
Rd
RegDst
Mux
Rs
ALUctr
RegWr
5
5
5
busA
W_Src
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
busB
Clk
MemWr
32
Mux
Mux
WrEn
Adr
Data In
32
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc
ExtOp
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3e Store Operations

• Mem Rrs SignExtimm16 lt- Rrt Example
  sw rt, rs, imm16

Rt
Rd
ALUctr
MemWr
W_Src
RegDst
Mux
Rs
Rt
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
busB
Clk
32
Mux
Mux
WrEn
Adr
Data In
32
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
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3f The Branch Instruction

• beq rs, rt, imm16
• memPC Fetch the instruction from memory
• Equal lt- Rrs Rrt Calculate the branch
  condition
• if (COND eq 0) Calculate the next instructions
  address
• PC lt- PC 4 ( SignExt(imm16) x 4 )
• else
• PC lt- PC 4

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Datapath for Branch Operations

• beq rs, rt, imm16 Datapath generates
  condition (equal)

Inst Address
nPC_sel
32
00
imm16
PC Ext
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Putting it All Together A Single Cycle Datapath
Instructionlt310gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Imm16
Rd
Rt
Rs
RegDst
ALUctr
MemtoReg
MemWr
nPC_sel
Equal
Rt
Rd
0
1
Rs
Rt
4
RegWr
5
5
5
busA
Rw
Ra
Rb

busW
00
32
32 32-bit Registers
ALU
0
32
busB
32
0
PC
32
Mux
Mux
Clk
32
WrEn
Adr
1
Clk
1
Data In
Extender
Data Memory
PC Ext
imm16
32
16
imm16
Clk
ExtOp
ALUSrc
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An Abstract View of the Critical Path

• Register file and ideal memory
• The CLK input is a factor ONLY during write
  operation
• During read operation, behave as combinational
  logic
• Address valid gt Output valid after access time.

Critical Path (Load Operation) PCs
Clk-to-Q Instruction Memorys Access Time
Register Files Access Time ALU to
Perform a 32-bit Add Data Memory Access
Time Setup Time for Register File Write
Clock Skew
Ideal Instruction Memory
Instruction
Rd
Rs
Rt
Imm
5
5
5
16
Instruction Address
A
Data Address
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
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Step 4 Given Datapath RTL -gt Control
Instructionlt310gt
Inst Memory
lt2125gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Adr
Op
Fun
Imm16
Rd
Rs
Rt
Control
ALUctr
MemtoReg
MemWr
nPC_sel
ALUSrc
RegDst
ExtOp
RegWr
Equal
DATA PATH
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Meaning of the Control Signals

• Rs, Rt, Rd and Imed16 hardwired into datapath
• nPC_sel 0 gt PC lt PC 4 1 gt PC lt PC 4
  SignExt(Im16) 00

nPC_sel
4
00
PC
Clk
imm16
PC Ext
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Meaning of the Control Signals

• MemWr write memory
• MemtoReg 1 gt Mem
• RegDst 0 gt rt 1 gt rd
• RegWr write dest register

• ExtOp zero, sign
• ALUsrc 0 gt regB 1 gt immed
• ALUctr add, sub, or

RegDst
ALUctr
MemtoReg
MemWr
Equal
Rt
Rd
0
1
Rs
Rt
RegWr
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
0
32
busB
32
0
32
Mux
Mux
Clk
32
WrEn
Adr
1
1
Data In
Extender
Data Memory
imm16
32
16
Clk
ExtOp
ALUSrc
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Control Signals
inst Register Transfer ADD Rrd lt Rrs
Rrt PC lt PC 4 ALUsrc RegB, ALUctr
add, RegDst rd, RegWr, nPC_sel
4 SUB Rrd lt Rrs Rrt PC lt PC
4 ALUsrc ___, Extop __, ALUctr ___, RegDst
___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel
__ ORi Rrt lt Rrs zero_ext(Imm16) PC lt
PC 4 ALUsrc ___, Extop __, ALUctr ___,
RegDst ___, RegWr(?), MemtoReg(?), MemWr(?),
nPC_sel __ LOAD Rrt lt MEM Rrs
sign_ext(Imm16) PC lt PC 4 ALUsrc ___,
Extop __, ALUctr ___, RegDst ___, RegWr(?),
MemtoReg(?), MemWr(?), nPC_sel __ STORE MEM
Rrs sign_ext(Imm16) lt Rrs PC lt PC
4 ALUsrc ___, Extop __, ALUctr ___, RegDst
___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel
__ BEQ if ( Rrs Rrt ) then PC lt PC
sign_ext(Imm16) 00 else PC lt PC 4 ALUsrc
___, Extop __, ALUctr ___, RegDst ___,
RegWr(?), MemtoReg(?), MemWr(?), nPC_sel __
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Control Signals
inst Register Transfer ADD Rrd lt Rrs
Rrt PC lt PC 4 ALUsrc RegB, ALUctr
add, RegDst rd, RegWr, nPC_sel
4 SUB Rrd lt Rrs Rrt PC lt PC
4 ALUsrc RegB, ALUctr sub, RegDst rd,
RegWr, nPC_sel 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Z, ALUctr or, RegDst rt, RegWr,
nPC_sel 4 LOAD Rrt lt MEM Rrs
sign_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Sn, ALUctr add, MemtoReg,
RegDst rt, RegWr, nPC_sel 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrs PC lt PC 4
ALUsrc Im, Extop Sn, ALUctr add, MemWr,
nPC_sel 4 BEQ if ( Rrs Rrt ) then PC
lt PC sign_ext(Imm16) 00 else PC lt PC
4 nPC_sel EQUAL, ALUctr sub
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Step 5 Logic for each control signal

• nPC_sel lt if (OP BEQ) then EQUAL else 0
• ALUsrc lt if (OP 000000) then regB else
  immed
• ALUctr lt if (OP 000000) then
  funct elseif (OP ORi) then OR elseif
  (OP BEQ) then sub else add
• ExtOp lt _____________
• MemWr lt _____________
• MemtoReg lt _____________
• RegWr lt_____________
• RegDst lt _____________

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Step 5 Logic for each control signal

• nPC_sel lt if (OP BEQ) then EQUAL else 0
• ALUsrc lt if (OP 000000) then regB else
  immed
• ALUctr lt if (OP 000000) then
  funct elseif (OP ORi) then OR
  elseif (OP BEQ) then sub else
  add
• ExtOp lt if (OP ORi) then zero else sign
• MemWr lt (OP Store)
• MemtoReg lt (OP Load)
• RegWr lt if ((OP Store) (OP BEQ)) then
  0 else 1
• RegDst lt if ((OP Load) (OP ORi)) then
  0 else 1

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Example Load Instruction
Instructionlt310gt
Inst Memory
lt2125gt
lt1620gt
lt1115gt
lt015gt
Adr
Imm16
Rd
Rt
Rs
RegDst
ALUctr
MemtoReg
MemWr
nPC_sel
Rt
Equal
Rd
rt
add
4
0
1
Rs
Rt
4
RegWr
5
5
5
busA
Rw
Ra
Rb

busW
00
32
32 32-bit Registers
ALU
0
32
busB
32
0
PC
32
Mux
Mux
Clk
32
WrEn
Adr
1
Clk
1
Data In
Extender
Data Memory
PC Ext
imm16
32
16
imm16
Clk
sign
ext
ExtOp
ALUSrc
32
An Abstract View of the Implementation
Control
Ideal Instruction Memory
Control Signals
Conditions
Instruction
Rd
Rs
Rt
5
5
5
Instruction Address
A
Data Address
Data Out
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
Datapath

• Logical vs. Physical Structure

33
A Real MIPS Datapath (CNS T0)
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Summary

• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic
• MIPS makes it easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates
• Single cycle datapath gt CPI1, CCT gt long