O%20Fortuna

1
O Fortuna

• O Fortune, just as the moon you vary your state
  always increasing or decreasing the detestable
  life now difficult and then easy with your games
  sharpens poverty, power dissolves like ice.
• Often great and empty, your revolving wheel, an
  evil state, vain health always dissolving,
  concealing and veiled you also strive for me now
  by game, a lost shirt I guiltily take because of
  you.
• Often my health and my virtue are now contrary
  for me, affected and defective always in torment
  In this hour without delay take the pulse of my
  heart, which through fate, she overthrows my
  strength weep all of you with me.

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17 November

• 5 classes to go
• No class on Tuesday 22 November
• Last 2 classes will be extra topics and exam
  review
• Interconnect and IO

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Final Exam

• Regular written examinations are required at the
  end of each term in all courses numbered below
  200, except those whose nature makes written
  examination unnecessary. Exceptions must have
  advance approval of the Provost. A final
  examination schedule is announced each semester,
  and no examination (except for laboratory
  sections) may be held at any time other than
  specified. No instructor shall give a quiz or
  assign a paper that is not a part of the
  equivalent of a current daily recitation within
  one week (five class days) preceding the final
  examination period.
• Final examinations for a full course should
  ordinarily cover two hours but should not exceed
  a period of three hours. Each student is required
  to subscribe his or her name to the following
  pledge or its equivalent on every paper "I
  hereby certify that during this examination I
  have neither given nor received aid." The
  instructor will not report a grade for any
  student whose examination paper lacks this
  pledge. Instead, he or she will register "no
  pledge" on the class grade report that is sent to
  the Office of the University Registrar.

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SoDoh!

• Our Final Exam will be Saturday 17 December from
  4PM to 7PM in (I guess) Ph 265.
• Dean of Students says notify your Community
  Director if you need to stay late in the dorms

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Interconnect Busses
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Goals of Interconnect

• Modularity
• Everything doesnt fit on a single chip (yet)
• Where to draw the lines?
• Minimize communication?
• Minimize cost?
• Maximize expandability?
• Expansion
• More processors
• More memory
• More devices

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Backplane Bus
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Issues in Interconnect

• Physical Interface
• Single wire
• Multiple wires
• Radio
• Light
• Protocol
• Sync/Async
• Master/Slave
• Access Control
• Time-Division Multiple Access
• Frequency-Division Multiple Access
• Code-Division Multiple Access

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Dawn of the Dumb Bus ISA EISA

• ISA (Original IBM PC Bus)
• Just take control and data signals from the CPU
  chip, buffer, and call it a bus

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Smarter Buses

• The function that buses serve is simple
• They allow movement of data from point to point
  via transactions
• They define rules for initiating and completing
  these transactions (PROTOCOLS)
• Terminology
• BUS MASTER a module who initiates a bus
  transaction
• BUS SLAVE a module who responds to a bus request
• BUS CYCLE The period from when a transaction is
  requested until it is served

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Typical Synchronous Bus Timing

• Why an asymmetric clock?
• Double duty data transitions on one edge,
  sampled on the other
• Assures hold times
• Asymmetric high/low phases maximizes transmission
  interval
• Allows for several round-trip bus delays so
  that ringing can die down

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A Simple Bus Transaction

• Master
• Acquires bus
• Asserts start, operation, and address
• Waits for bus to answer
• Slaves
• Monitors every start
• Check address
• If meant for me
• Look at bus operation
• Do operation
• Signal finish of cycle
• Bus
• Monitors start
• Count down
• If no one answers before counter reaches 0, then
  time out

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Multiple Bus Masters

• Problem Acquiring the bus. How to become a bus
  master?
• Example Daisy Chain Arbitration

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Bus Arbitration Issues

• Fairness Given uniform requests, bus cycles
  should be divided evenly among modules
• Bounded wait There should be an upper bound on
  how long a module as to wait between requesting
  and receiving a grant
• Utilization Arbitration scheme should allow for
  maximum bus performance
• Scalability Fixed-cost per module (both in
  terms of arbitration H/W and arbitration time

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Ethernet
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USB

• Universal Serial Bus
• Provides power and signal
• A single host connects to multiple devices
• Devices are given 7 bit addresses whenplugged in
• Controller polls them round-robin
• 1.5Mbit/s for USB 1, up to 486Mbit/s for USB 2.
• Hot pluggable
• Plug and Play

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Firewire

• IEEE 1394
• Serial bus plus power
• Multiple masters
• Up to 800Mbit/s
• Hot pluggable
• Plug and Play

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Interrupts

• How does the CPU manage SLOW I/O devices?
• Programmed I/O
• Interrupt Driven I/O

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Polling
Advantages Simple No surprises Processor in
full control Disadvantages Polling can waste
lots of time
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Interrupt Driven I/O
Advantage CPU only bothered when actually
needed Disadvantage Can occur at surprising or
inconvenient times Have to save and restore state
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MIPS Exceptions

• Reset
• Hardware Errors (Check, Bus Error, Cache Error)
• External Interrupt (6 inputs)
• Address Error
• Reserved Instruction
• TLB Miss
• System Call
• Breakpoint
• Trap
• Integer Overflow
• Floating Point Error
• Timer
• And a few more

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Exception Processing

• EPC gets address of faulty instruction or of next
  instruction depending on type of exception
• Switch to kernel mode
• Jump to a new location based on type of exception
• PC ? FFFF FFFF BFC0 0000 for Reset
• PC ? FFFF FFFF BFC0 0300 for Hardware error
• PC ? FFFF FFFF BFC0 0380 for external interrupts
• PC ? FFFF FFFF BFC0 0400 for
• Save registers
• Examine the cause register to find out why you
  came here
• Branch to code to do the right thing

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Magnetic Disk

• Long term, nonvolatile storage
• Large, inexpensive, and slow
• Rotating platter(s) coated with magnetic material
• Use a movable read/write head to access

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Magnetic Disk Organization

• Cylinder All tracks under head with arm in a
  fixed position
• Read/Write time has 3 components
• Seek time to move the arm
• Rotational latency wait for the desired sector
  to come by
• Transfer time transfer bits

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Typical Disk Times

• Average Seek 8ms to 12ms
• Sum of all possible seek / number of possible
  seeks
• Locality reduces this to maybe only 25 of
  average number
• Rotational Latency
• At 5400 RPM ? 11 ms
• At 7200 RPM ? 8 ms
• At 10000 RPM ? 6ms
• Transfer time depends on
• Transfer size (typical 512 bytes)
• Rotation speed
• Recording density
• Diameter
• Typical values 10 to 30MBytes per second

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Classes to go
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