The Verilog Hardware Description Language

1
332437 Lecture 6Verilog Behavioral Modeling and
Concurrency

• Behavioral Modeling
• Concurrency
• Always Blocks and Sensitivity Lists
• Initial Statements
• Procedural Specification of Comb. Logic
• Simulation Control and Files
• Summary

Material from The Verilog Hardware Description
Language, By Thomas and Moorby, Kluwer Academic
Publishers
2
Dataflow, Behavioral, and Logic Descriptions

• Differences
• Process is a hardware description that runs in
  parallel with other processes (usually activated
  by a variable change and a clock change)
• Dataflow descriptions do not use processes
• Behavioral ones do
• Boolean equation description
• Too cumbersome
• Structural hardware description
• Very cumbersome want to generate this from data
  flow, behavioral, or equation description
• Do not want to generate this directly

3
Behavioral Modeling

• Procedural statements are used
• Statements using always Verilog construct
• Can specify both combinational and sequential
  circuits
• Normally dont think of procedural stuff as
  logic
• They look like C mix of ifs, case statements,
  assignments
• but there is a semantic interpretation to put
  on them to allow them to be used for simulation
  and synthesis (giving equivalent results)
• Current technology
• You can do combinational (and later, sequential)
  design
• Sizable designs can take hours days to run
• Companies pay 50K - 80K per copy for such
  software
• This aint shrink-wrap software!
• The software we use is more like 15-20K

4
Behavioral Constructs

• Behavioral descriptions are introduced by initial
  and always statements
• Points
• They all execute concurrently
• They contain procedural statements like
  if-then-else, case, loops, functions,

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Statements, Registers and Wires
Multi-bit registers and wires

• Registers
• Define storage, can be 1-bit or more
• Can only be changed by assigning value to them on
  the left-hand side of a behavioral expression.
• Wires (actually nets)
• Electrically connect things together
• Can be used on the right-hand side of an
  expression
• Thus we can tie primitive gates and behavioral
  blocks together!
• Statements
• left-hand side right-hand side
• left-hand side must be a register
• Four-valued logic

Logic with registers and wires
module silly (q, r) input 30 q, r
reg 30 a, b always begin a (b
r) q q b end endmodule
Cant do why?
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Two Initial Statements?
initial begin a 0 b 0 5 b 1 13 a
1 end initial begin out 1 10 out 0
8 out 1 end
arbitrary

• Things to note
• Which initial statement starts first?
• What are the values of a, b, and out when the
  simulation starts?
• These appear to be executing concurrently (at the
  same time). Are they?

x
Yes, in simulated time
7
Behavioral Statements

• if-then-else
• What you would expect, except that its doing
  4-valued logic. 1 is interpreted as True 0, x,
  and z are interpreted as False
• case
• What you would expect, except that its doing
  4-valued logic
• If selector is 2 bits, there are 42 possible
  case-items to select between
• There is no break statement it is assumed.
• Sized, 4-valued constants
• The first number is the number of bits, the
  letter is the base of the following number that
  will be converted into the bits.
• 8b00x0zx10

if (select 1) f in1 else f in0
case (selector) 2b00 a b c 2b01 q r
s 2bx1 r 5 default r 0 endcase
assume f, a, q, and r are registers for this slide
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Behavioral Statements

• Loops
• There are some restrictions on using these for
  synthesis
• For this course dont.
• They are mentioned here for use in test modules
• Two main ones for and while
• Just like in C
• There is also repeat and forever see the book

reg 40 testOutput, i for (i 0 i lt 15 i
i 1) begin testOutput i 20 end
reg 40 testOutput, i i 0 while (i lt 15)
begin testOutput i 20 i i 1 end
Important Loops must have a delay operator (or
as well see later, an _at_ or wait(FALSE)).
Otherwise, the simulator never stops executing
them.
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Concurrent Constructs

• We already saw delay
• Others
• _at_ Waiting for a change in a value used in
  synthesis
• _at_ (var) w 4
• This says wait for var to change from its current
  value. When it does, resume execution of the
  statement by setting w 4.
• Wait Waiting for a value to be a certain level
  not used in synthesis
• wait (f 0) q 3
• This says that if f is equal to zero, then
  continue executing and set q 3.
• But if f is not equal to zero, then suspend
  execution until it does. When it does, this
  statement resumes by setting q 3.
• Why are these concurrent?
• While one model waits for something, that
  something happens (concurrently) in another model

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FAQs Behavioral Model Execution

• How does an always or initial statement start
• That just happens at the start of simulation
  arbitrary order
• Once executing, what stops it?
• Executing either a delay, _at_event, or wait
  (FALSE).
• All always blocks need to have at least one of
  these. Otherwise, the simulator will never stop
  running the model (its an infinite loop!)

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More FAQs About Concurrency

• How long will it stay stopped?
• Until the condition that stopped it has been
  resolved
• delay until the delay time has been reached
• _at_(var) until var changes
• wait(var) until var becomes TRUE
• Does time pass when a behavioral model is
  executing?
• No. The statements (if, case, etc) execute in
  zero time.
• Time passes when the model stops for , _at_, or
  wait.
• Will an always stop looping?
• No. But an initial will only execute once.

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A Combinational Circuit

• Using behavioral constructs
• Logic for a simple MUX is specified procedurally
  here
• This example is synthesizable

Read this as follows Wait for any change on sel,
b, or c, then execute the begin-end block
containing the if. Then wait for another change.
module MUX (f, sel, b, c) output reg f
input sel, b, c always _at_ (sel or b or
c) begin if (sel 1) f
b else f c end endmodule
This if functionally describes the MUX
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Huh? Is It Really Correct?

• WWWWaaaaaiiiiiitttt a minute?
• Wheres the register?
• The synthesis tool figures out that this is a
  combinational circuit. Therefore, it doesnt
  need a register.
• The register is there as an artifact of the
  description things on the left-hand side have
  to be registers.
• How does it figure out that this is
  combinational?
• The output is only a function of the inputs (and
  not of previous values)
• Anytime an input changes, the output is
  re-evaluated
• From outside the module, could you tell that
  there is a register in there?
• Does the loop have state?

?
module MUX (f, sel, b, c) output reg
f input sel, b, c always _at_ (sel or b or
c) begin if (sel 1) f
b else f c end endmodule
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Logic vs. Behavioral Verilog Code

• Logic Verilog

• Behavioral Verilog
• Less trouble to write

module MUX (f, a, b, sel) output f input a, b,
sel and 5 g1 (f1, a, nsel), g2 (f2, b,
sel) or 5 g3 (f, f1, f2) not g4 (nsel,
sel) endmodule
module MUX (f, sel, b, c) output reg
f input sel, b, c always _at_ (sel or b or
c) begin if (sel 1) f
b else f c end endmodule
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Synthesis Template

• Using procedural statements in Verilog
• Logic is specified in always statements
  (Initial statements are not allowed).
• Each always statement turns into Boolean
  functions

You have to declare the combinational outputs
like this, for synthesis. i.e., tool needs to
think you are putting these computed outputs
someplace.
module blah (output reg f, input a, b,
c) always _at_ (a or b or c) begin stuff...
stuff... stuff... end endmodule
You have to list all the blocks inputs here in
the sensitivity list. () also works!
Actually do logic in here. There are a bunch of
subtle rules to ensure that synthesis wont mess
this up... Well see how
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How? A Few Definitions

• There are some restrictions on specification
• Input set of an always statement the set of
  all variables that are used on the right-hand
  side of procedural assignments or in
  conditionals. i.e. anything sourced.
• Sensitivity list of an always statement the
  set of all names that appear in the event (_at_)
  list.

module mux (output reg f, input sel, b,
c) always _at_ (sel or b or c) begin if (sel
1) f b else f
c end endmodule
The elements in these lists are
input sel, b, c
sensitivity sel, b, c
No coincidence here a combinational circuit is
sensitive to its inputs
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More Definitions...

• A control path of an always statement a
  sequence of operations performed when executing
  the always statement
• Combinational output of an always statement a
  variable (or variables) assigned to in every
  control path

What are they here...
module mux (output reg f, input sel, b,
c) always _at_ (sel or b or c) begin if
(sel 1) f b else f
c end endmodule
Control paths through then and else of if
statement
Combinational output f
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The Basic Rules

• The rules for specifying combinational logic
  using procedural statements
• Every element of the input set must be in the
  sensitivity list
• The combinational output must be assigned in
  every control path

module MUX (output reg f, input sel, b,
c) always _at_ (sel or b or c) begin if
(sel 1) f b else f
c end endmodule
So, were saying that if any input changes, then
the output is re-evaluated. Thats the
definition of combinational logic.
Walking this narrow line allows you to specify
and synthesize combinational logic
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What If You Mess Up?

• If you dont follow the rules...?
• Verilog assumes you are trying to do something
  clever with the timing
• Its legal, but it wont be combinational
• The rules for what it does make sense but not
  yet for us.

youre dead meat
This says as long as a1, then f follows b.
(i.e., when b changes, so does f.) But, when
a0, f remembers the old value of b.
Combinational circuits dont remember anything!
module blah (output reg f, g input a, b,
c) always _at_ (a or b or c) begin if (a
1) f b else g c end endmodule
Whats wrong?
f doesnt appear in every control path in the
always block (neither does g).
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Typical Style

• Your Verilog for combinational stuff will look
  like this
• Yes...its a pretty restricted subset of the
  language...

module blah (ltoutput namesgt, ltinput
namesgt) output ltoutput namesgt input ltinput
namesgt reg ltoutput namesgt always _at_
(ltnames of all input varsgt) begin lt LHS
RHS assignmentsgt lt if ... else
statementsgt lt case statements gt end endmodule
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A Difficulty Assigning in Control Paths

• Assigning in every control path
• If the function is complex, you dont know if you
  assigned to the outputs in every control path.
• So, set all outputs to some known value (zero
  here) and write the code to set them to other
  values as needed.
• Synthesis tools will figure it out, but try to
  write clearly.

always _at_(coke or cola) begin if (coke) blah1
1 else if (cola gt 2b01) blah2 coke else
if ( end
always _at_(coke or cola) begin blah1 0 blah2
0 if (coke) blah1 1 else if (cola gt
2b01) blah2 coke else if ( end
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Using a Case Statement

• Truth table method
• List each input combination
• Assign to output(s) in each case item.
• Concatenation
• a, b, c concatenates a, b, and c together,
  considering them as a single item
• Example
• a 4b0111
• b 6b 1x0001
• c 2bzx
• then a, b, c 12b01111x0001zx

module fred (output reg f, input a, b,
c) always _at_ (a or b or c) case (a, b,
c) 3b000 f 1b0 3b001 f
1b1 3b010 f 1b1 3b011 f
1b1 3b100 f 1b1 3b101 f
1b0 3b110 f 1b0 3b111 f
1b1 endcase endmodule
Check the rules
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How About a Case Statement Example?
module fred (output reg f, input a, b,
c) always _at_ (a or b or c) case (a, b,
c) 3b000 f 1b0 3b001 f
1b1 3b010 f 1b1 3b011 f
1b1 3b100 f 1b1 3b101 f
1b0 3b110 f 1b0 3b111 f
1b1 endcase endmodule
check the rules
module fred (output reg f, input a, b,
c) always _at_ (a or b or c) case (a, b,
c) 3b000 f 1b0 3b101 f
1b0 3b110 f 1b0 default f
1b1 endcase endmodule
Could put a function here too
Important every control path is specified
x and z not considered in case enumeration!
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Dont Cares in Synthesis

• Rules
• You cant say if (a 1bx) this has
  meaning in simulation, but not in synthesis.
• However, an unknown x on the right-hand side will
  be interpreted as a dont care.

module caseExample (output reg f, input a,
b, c) always _at_ (a or b or c) case (a, b,
c) 3b001 f 1b1 3b010 f
1b1 3b011 f 1b1 3b100 f
1b1 3b111 f 1b1 3b110 f
1b0 default f 1bx endcase endmodule
ab
00 01 11 10
c
0 1
0
1
1
x
1
1
1
x
The inverse function was implemented xs taken
as ones.
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Alternatively
module fred1 (output reg f, input a, b,
c) always _at_ (a or b or c) f (a b
c) endmodule

• These arent quite equivalent to the previous
  slidewhy?

module fred3 (output reg f, input a, b,
c) always _at_ (a or b or c) begin if (c
0) f ab else f 1b1 end endmodu
le
module fred2 (output reg f, input a, b,
c) always _at_ (a or b or c) f a c
b endmodule
ab
00 01 11 10
c
0 1
0
1
1
x
1
1
1
x
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Two Input Bits, Three Output Bits
reg 10 newJ reg out input i, 10
j always _at_(i or j) case (j) 2b00 begin new
J (i 0) ? 2b00 2b01 out 0 end
2b01 begin newJ (i 0) ? 2b10
2b01 out 1 end 2b10 begin newJ
2b00 out 0 end default
begin newJ 2b00 out
1'bx end endcase
Works like the C conditional operator. (expr)
? a b If the expr is true, then the resulting
value is a, else its b.
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Signal Assignment Statement

• equals lt (a b) ? 1b1 1b0
• Assigns values to equals signal, possibly after a
  delay
• (a b) Compares all 4 bits of a with all 4
  bits of b
• Compare bitwise left to right
• Big problem for you with lt operator
• Assignment does not happen immediately!
• Example
• z lt 0 if (a 1b1) z lt 1 // This doesnt
  work
• Does not mean the same thing as
• Z 0 if (a 1b1) z 1 // This works

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Port Bit Numbering Methods

• Declarations of a and b
• input 30 a, 30 b
• Declares a b as ports descending index
  declaration needed
• Highest index bit Most Significant
• 0th bit Least Significant
• Little End Machine like Compaq Alpha
• Other way
• input 03 a, b
• Highest index bit Least Significant
• Lowest index bit (0) Most significant
• Big End Machine like IBM System/360, IBM
  ES/9000

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What about Time Delay?

• Could we have described the module as shown here?
• Note the delays. There is a different delay from
  the b input than from the c input.
• Yes, you could write this
• But,
• Synthesis tools will ignore the time delays.
• Generally, they try to minimize the propagation
  from any combinational input to any combinational
  output in the system.

module mux (output reg f, input sel, b,
c) always _at_ (sel or b or c) begin if (sel
1) 5 f b else 88 f
c end endmodule
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Model Organization

• Heres an always block for a combinational
  function.
• What Boolean functions can it model?
• Can I have more than one of these always blocks
  in a module?
• Can two separate always blocks calculate
  function f?
• No

always _at_(b1 or b2 or b3) begin yadda yadda end
Yes
Only those with inputs b1, b2, and b3
module xyzzy (ports) always _at_(b1 or b2 or
b3) begin q b1 b2 b3 r b2
b3 end always _at_(r1 or b2 or b3) begin s
yadda yadda yadda end
module xyzzy (ports) always _at_(b1 or b2 or
b3) begin f yadda end always _at_(r1 or r2 or
r3) begin f yadda yadda end
Nope!
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Displaying and Monitoring Signals

• More than modeling hardware
• monitor give it a list of variables. When one
  of them changes, it prints the information. Can
  only have one of these active at a time. e.g.
• monitor (time,,, ab, bb, sumb, cOutb,
  a, b, sum, cOut)
• The above will print 2 a0, b0, sum0,
  cOut0ltreturngt
• display() sort of like printf() in C
• display (Hello, world h, hexvalue)

extra commas print spaces
b is binary (also, h, d and others)
What if what you print has the value x or z?
newline automatically included
display contents of data item called hexvalue
using hex digits (0-9,A-F)
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Files

• Contain values, used to read in circuit stimuli
  and to write out test benches
• Preferred way to test and debug the design with
  the simulator
• fopen (name of file) -- returns file
  descriptor, which can be used to access the file
• fclose (descriptor) -- closes the file
  associated with descriptor
• fwrite (descriptor, parameters as in write
  command)
• readmemx (file name, memory name, start
  address, finish address)
• x can be b (binary) or x (hexadecimal) loads
  specified memory with data from file
• fdisplay (descriptor, parameters as in display
  command)
• fmonitor (descriptor, parameters as in monitor
  command)
• fstrobe (descriptor, parameters as in strobe
  command)
• Data written to file only when simulation time
  advances

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Summary

• Behavioral Modeling
• Concurrency
• Always Blocks and Sensitivity Lists
• Initial Statements
• Procedural Specification of Comb. Logic
• Simulation Control and Files
• Summary