Section 4'4 IBM PC, PS IO Map

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• Section 4.4 IBM PC, PS I/O Map
• Designers of the IBM PC decided to make full use
  of I/O instructions.
• This led to assigning different port addresses
  to various peripheral chips and devices connected
  to the 8088 CPU.
• Table 4-2 provides the port addresses of the
  original 8088 PC/XT and compatibles.

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• Use of the 8255 in the IBM PC/XT
• The 8255 in the IBM PC/XT and compatibles is an
  IC chip used primarily for inputting and
  outputting data to and from ports.

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• Port A
• In the early models of the IBM PC and XT input
  from the keyboard and input from DIP switches.
• DIP switches were used to inform the PC about
  add-on peripherals such as the amount of RAM,
  type of monitor, and the number of disk drives.
• The DIP switch settings were read during the
  running of BIOS and stored internally.
• After that there is no need to read them again
  thereafter the system will use port A for
  receiving bytes of data from the keyboard.
• Nowadays DIP switches are changed to CMOS RAM.

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Port B Port B is assigned port address 61H and
initialized as an output port.
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Port C Port C is programmed as input and assigned
port address 62H
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• Control word calculation
• In the IBM PC/XT, the three ports in the 8255
  are configured with port A as input, port B as
  output, port CL as input, and port CU as input.
• MOV AL, 99H
• OUT 63H, AL
• It is best to see your computer technical
  reference manual to get the configuration for
  your PC.

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• Section 4.5 80286 AT Computers and ISA Bus I/O
  Ports
• Interfacing 8-bit peripherals to a 16-bit data
  bus
• The data for even-address ports is carried on
  data bus D0-D7 and data for odd address ports is
  carried on D8-D15.
• Simply use two separate PPI devices, one is used
  for odd addresses, and one for even addresses.
  For example, in a design using this method, if
  port 74H is assigned to port A of the 8255, the
  port B has the address 76H and port C the address
  78H, and so on.
• The second solution is to connect all 8-bit
  peripheral ports to data bus D0-D7. This is
  exactly what IBM PC/AT designers, and indeed all
  clone makers of the 80x86 ISA bus.
• OUT 75H, AL
• Hi/Lo byte copier

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• Case 1 Outputting a byte to odd-addressed ports
• To write a byte to an odd-addressed port, the
  CPU provides the data on its upper data bus
  (D8-D15) and makes A01, and BHE0
• Case 2 Inputting a byte from odd-addressed ports
• To read a byte from an odd-addressed port, the
  CPU expects to receive the data on its upper data
  bus (D8-D15) and makes A01, and BHE0
• AT bus 80x86 computers and ISA bus
• When the CPU communicates with an expansion slot,
  it can only use an 8- or 16-bit data bus. To
  access a CPUs entire 32-bit data bus through the
  expansion slot, one must use the EISA bus, IBM
  Micro Channel, or local bus-type computers.
• The ISA bus speed is limited to 8 MHz. Need to
  insert wait states.

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• I/O bus cycle and bandwidth
• In communications between the CPU and I/O ports,
  there are occasions when an I/O device is slow
  and cannot respond to the CPUs normal speed.
• In such a situation, wait states must be
  inserted into the I/O cycle.
• 8088/86 and PC/XT I/O bus cycle
• The 8088/86 microprocessor provides only 4
  clocks for the I/O cycle if it is designed with 0
  wait state.
• 286 and ISA bus I/O cycle time
• The 80286 and all higher microprocessors (386,
  486, etc.) have two clocks for the I/O cycle time
  when they are designed with 0 WS.
• To interface with slow I/O devices, one must
  insert wait state into the I/O cycle time to
  match the device speed.

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• Section 4.6 Interfacing I/O to PC, XT, AT, PS and
  ISA Computers
• Absolute vs. linear select address decoding
• In addresses, either all of them or a selected
  number of them can be decoded.
• If all the address lines are decoded, it is
  called absolute decoding.
• If only selected address buses are used for
  decoding, it is linear select decoding (also
  called partial address decoding).
• Linear select is cheaper.
• The disadvantage is that it creates what are
  called aliases the same port with multiple
  addresses.

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• Buffering selected I/O address ranges
• To buffer a range of I/O addresses, the 74LS245
  must be gated with the decoder for the I/O
  address range.