LDRDDOE Project Layouts

1
LDRD/DOE Project Layouts
DOE PHX chip 512 channels Mini-strips 50 mm x
2-13 mm wide
LDRD FPIX chip 128x22 channels Pixel silicon
50 x 400 mm pixels
?

• 8 chips/layer 1, 11 chips/layer in back 3 layers
• 48 towers/layer, 4 layers, 2 arms
• 3936 chips, 384/96 boards (11/41 chips/board)
  (2M channels)

• 8 chips wide 7 cm
• 24 chips high 15 cm
• 1-4 phi positions, 4 layers
• 768N chips

2
Front-end chip?Interface Board
Arcnet (FPGA program., chip download)

• Serial download to chips
• Pass beam clock

?
3
I/O Requirements for Interface Board

• Chip?Interface Board
• (1,2,4 readout lines)(11,41,96chips) 11, 22,
  44 lines (pairs)
• Serial Download to Chips
• 5 lines per 8-chips (pairs) (from Guilherme)
• Clock 1 line per chip (pairs) (from Guilherme)
• TFC interface 20 lines
• DCM interface 20 lines
• Output to Lvl-1 ? John says they expect to
  receive the same data streams that the interface
  board receives
• ARCNet (or equivalent) for downloading chips/FPGA
• Pulser input(s) ?

4
Interface Board FPGA Code Requirements

• Code to initialize chips Currently have code
  from Fermilab which does this, but probably want
  to convert to straight VHDL.
• De-serialize data stream coming from chips if
  more than one readout line, combine lines to make
  data word, strip pieces off needed for buffer
• Buffer Space
• Need to store 64 clocks worth of data
• May require up to 50kbits for AuAu events
  (modest, if memory management is smart enough.
  Could be much more if not done right?)
• Read/Write asynchronous (though one clock is
  expected to be integral multiple of other)
• Lvl-1 Accepts Must be able to handle up to 5
  lvl-1 accepts
• Data Output and packaging
• Upon lvl-1, retrieve data from appropriate clock,
  package, and ship to DCM
• Will be variable-length data packets (?)
• Upon every clock, ship data from that clock to
  Lvl-1 decision maker, with latencyltN clocks
• Data Integrity Checks
• Keep track of synch data words and check for
  apparent missed bits
• Need to tag data or respond otherwise if chip
  appears to have fallen behind and/or data has
  maxed out buffer space so may be incomplete
• Data size limit (from Chi) (50ms)/(25ns/16 bit
  word) 2000 16 bit words

5
LDRD/DOE Project Numbers
6
Where we are

• FSSR chip and associated DAQ up and running in
  lab
• Are to receive FPIXsiliconHDI in January
• Are to receive 6-chip FSSR setup soon (?)
• Have FPGA code which takes care of initializing
  chip, reads data back from chip and dumps into PC
  DAQ for event crunching
• Source code to DAQ FPGA which can allow us to
  change clocks, etc.
• Have FPGA development board(s) which can be
  played with to develop some FPGA code
• Have Mini-DAQ at LANL, but needs computer, has
  not been set up yet
• Assume we can get some TFC, DCM copper-fiber
  translator boards relatively easily to get
  optical links when we are ready for that

7
Possible Development Timeline FPGA Development
board initially, switching to real board
Input to Board
Data Management on Board
Data Out from Board
Design and Prototype Real Board
Develop Buffer for 1 chip
Develop Our Data Deserializer
Dump Data to PC (initially just buffer dump?)
Accept a trigger in (generic)
Grab data from BCO of interest and dump, with
full buff.
Expand to multiple chips
Switch to real board for software development
Get trigger from TFC module
Add packaging for DCM

• Misc
• Data in from chip immediately or some simulated
  data?
• Convert chip download code to VHDL (and add to
  this code)
• Where to add various clock passing
• Where to add lvl-1 out

Add copper/fiber translater and DCM
8
Discussion

• Pieces of FPGA code required and best graded
  approach to writing code
• Best buffering scheme
• Number of chips to gang together/interface board.
  1 FPGA/board or should multiple FPGAs per board
  be considered?
• Interfacing to Lvl-1 AND DCM imply different
  coding or not, additional requirements
• How to handle BUSY
• Distributing work of interface card

9
Backups
10
Occupancies from AuAu (Hubert/Dave)
7/cm2?0.7 occupancy at innermost radii (50 mm x
2 mm strips)
11
Receiver End Block Diagram A possible starting
point from Chi
Sort FSSR data according to beam crossing number
FSSR serial data in
Sort in coming data according to the BC number
64 buffers cover 6.4 microsec Buffer can be
construct 4Kbits block in FPGA
4ns R/W Clk
Data to DCM if triggered
Data to L1
Each block has to have read/write counter
12
(No Transcript)
13
FPIX/PHX chips

• FPIX Fermilab-developed chip for BTEV. Would
  make a production run for LDRD project
• PHX modified FPIX chip which has channels which
  match the full FVTX detector geometry (128x22
  channels ? 512 channels)
• Serial download to chip initializes
• Number of readout lines/chip
• Thresholds (0-7) (one per chip)
• Optionally mask out channels
• Pulse injection (on some chips)
• Shaping time
• ?
• Data out from chip
• 2816/512 channels per FPIX/PHX chip
• Push system, 140 Mbps per readout line, 1,2,4 or
  6 lines/chip possible
• 24 bit words

14
FPIX State Machines