DCD company and products presentation

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OVERVIEW

• The Digital Core Design UART Cores are a family
  of configurable, synthesizable soft cores,
  compatible with industry standard UARTS,
  realizing the asynchronoous serial transmission
  with or without FIFO.
• The DCD UART Cores covers all available types of
  UARTs, assuring a programing flexibility.
• All DCD UARTS gives programmers features like
• Receiver and Transmitter FIFOs
• DMA support
• Modem control
• Software / hardware data flow control
• 5-, 6-, 7-, or 8-bit characters

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CPU FEATURES

• D16450 Configurable UART Core with modem
  suport.
• D16550 Configurable UART Core with 16 levels
  deep FIFOs and modem support.
• D16750 Configurable UART Core with 16/64 (up
  to 512) levels deep FIFOs, hardware data flow
  control, and modem support.
• D16752 Configurable Dual channel UART Core
  with 16/64 (up to 512) levels deep FIFOs,
  software and hardware data flow control, modem
  support.

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KEY FEATURES

• Software compatible with industry standards
• Configuration capability
• Separate configurable BAUD clock line
• Majority Voting Logic
• Adds or deletes standard asynchronous
  communication bits (start, stop, and parity) to
  or from the serial data
• Independently controlled transmit, receive, line
  status, and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR, DTR, RI,
  and DCD)

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KEY FEATURES

• Fully programmable serial-interface
  characteristics
• 5-, 6-, 7-, or 8-bit characters
• Even, odd, or no-parity bit generation and
  detection
• 1-, 1½-, or 2-stop bit generation
• Internal baud generator
• Complete status reporting capabilities
• Line break generation and detection. Internal
  diagnostic capabilities
• Loop-back controls for communications link fault
  isolation
• Break, parity, overrun, framing error simulation

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KEY FEATURES

• Software compatible with industry standards
• Configuration capability
• FIFO size
• RCLK, BAUDCLK lines
• Modem support
• Separate configurable BAUD clock line allows
  to setup correct transmission speed

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DESIGN FEATURES

• Full prioritized interrupt system controls.
• Fully synthesizable.
• Static synchronous design and no internal
  tri-states.
• Bidirectional buses split into two separate
  busses.
• Interface allows to use any type of Dual Ported
  RAM as a FIFO all FIFO control logic
  implemented inside the Core.
• Asynchronous interface replaced by equivalent
  synchronous one.
• All internal latches replaced by equivalent
  registers.

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APPLICATIONS

• Serial Data communication applications.
• Modem interface.
• Embedded microprocessor boards.

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CONFIGURABILITY
Easy core configuration with constants in Core
package
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CONFIGURATIONS
Easy selection from few typical configurations
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DELIVERABLES

• Source code
• VHDL Source Code or/and
• VERILOG Source Code or/and
• Encrypted, or plain text EDIF netlist
• VHDL VERILOG test bench environment
• Active-HDL automatic simulation macros
• ModelSim automatic simulation macros
• Tests with reference responses
• Technical documentation
• Installation notes
• HDL core specification
• Datasheet
• Synthesis scripts
• Example application

VHDL Verilog
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APROVEMENTS

• All DCD UART IP Cores Bus controllers has been
  sucessfully implemented in all major FPGA
  technologies, and got particular aproovements
  stams from
• ALTERA
• XILINX
• LATTICE

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