CSECE 365 Computer Architecture

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CS/ECE 365 Computer Architecture

• Soundararajan Ezekiel
• Department of Computer Science
• Ohio Northern University

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Lecture 6

• Read chapter 3
• Quiz 2 on chapter 3 on Monday
• H.W 2 out today Due Next WED
• Lab 1 is out today

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Review

• how the architect can help the compiler writer
• compiler writers are working under their own
  corollary of basic principle in architecture
• make the frequent case fast and rare case correct
• this means if you classify which is rare and
  frequent and if the code is straightforward then
  the quality of the code for rare case may not be
  very important BUT it must be correct

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Cont

• regularity--3 primary components of instruction
  set-- operation, data type, and addressing
  modes--- these 3 should be orthogonal
• 2 aspects of architecture is orthogonal gt they
  are independent
• example operations and addressing mode are
  orthogonal gt for every operations to which a
  certain addressing mode can be applied

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• provide primitives not solutions
• simplify trade offs among alternatives
• figuring out what instruction sequence will be
  best for every segment of code that arises.

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Ex

• Modern programming languages permit the
  definition of data structure that are arbitrary
  compositions of scalars, arrays, records, and
  pointers.
• In principle it is possible to define an array of
  records, a component of which is a pointer to a
  record containing an array of arrays of yet
  another kind of record.

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Continue

• Accessing a component at the bottom level of this
  structure involves a lengthy sequence of
  operations
• Because the interaction among the block
  structure, recursive procedures,and by reference
  parameters passing, finding the base address of
  such address can equally complex,

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Instruction Set Architecture ISA

• Interface between Hardware and Software

Assembly Language
Application Software
OS
compiler
Instruction set Architecture ISA
Instruction set processor
I/O System
Machine Language
Digital design
Circuit design
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Assembly Language

• Interface the architecture presents to user,
  compiler and operating system
• Low level instructions that use the datapath and
  memeory to perform basic type of operations
• arithmetic add, sub, mul div
• logical and or shift
• data transfer load store
• (un)conditional branch jump, branch on condition

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Instruction set Architecture--Overview

• Architecture whats visible to the program
  about the machine
• Not everything in the deep implementation is
  visible
• the name for this invisible stuff is the
  implementation
• A big piece of the ISA assembly language
  structure
• primitives instructions, execute sequentially,
  atmoically

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Todays Menu

• other ISA issues
• Branch/Jump instructions
• Procedure calls
• Addressing Modes
• Array vs pointers
• MIPS Architecture Summary

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Control(Instruction Sequencing)

• Decision Making instruction
• these instructions alter the control flow
• Means they change the next instruction to be
  executed
• MIPS conditional branch instruction
• bne t0, t1, Label
• beq t0, t1, Label
• example if(ij) hij
• bne s0, s1, Label
• add s3,s0,s1

Branch here if s0 not equal to s1
Label ..
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• MIPS unconditional branch instructions
• j label
• Example
• if(i!j)
• hIj
• else
• hI-j

beq s4,s5,Lab1 add s3, s4,s5 j Lab2
Lab1 sub s3,s4,s5
Lab2
OK, so with these -- Can you build a simple for
(..) loop?
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Branch instruction

• Exist because we need to change the program
  counter
• if (ab) c1
• else c2
• bne (branch not equal )compares regs and branches
  if reg not equal to
• j (jump) goto address, unconditional branch
• Assume R5a R6b R7c
• Add Mnemonic
  description (comment)
• 0x00 bne R5,R6 0x0c if (r51r6)goto
  0x0c
• 0x04 addi R7,R0, 1 R7lt---10
• 0x08 j 0x10 goto 0x10
• 0x0C addi R7,R0,2 R7lt---20
• 0x10

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• branch instruction end up the way we implement
  C-style loops
• for(j0jlt10j)
• bbj
• assume R5j, R6b
• Add Mnemonic
  description (comment)
• 0x00 addi R5,R0,0 R5lt----00
• 0x04 addi R1,R0, 10 R1lt---010
• 0x08 beq R5,R1, 0x14 if (R510)goto 0x14
• 0x1C add R6,R6,R5 R7lt---20
• 0x10 j 0x08 goto 0x08
• 0x14 pop out of loop,
  continue

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Address in Branches and Jumps

• Instructions
• bne t4,t5, Label Next instruction is at
  Label if t4!4t5
• beg t4, t5, Label Next instruction is at
  Label if t4t5
• j Label next instruction is
  at Label
• Formats

I
op
rs
rt
16 bit address
J
26 bit address
op
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conditional branch distance
Distribution of displacement for PC-relative
branches in instruction, about 75 of the
branches are in the forward direction
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conditional branch addressing
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DLX (pronounced Deluxe)Architecture

• first mythical computer MIX
• first polyunsaturated computer
• it has an identifying number 1009
• 16 actual computers which are very similar to MIX
  on which MIX can be easily simulated then
  averaging their numbers with equal wt

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• 3606507097070U3SS8011071604G20b220S2000
  920601H800PDP-411)/16 1009
• the same number may be obtained in a simpler way
  by taking Roman numerals
• Donald Knuth, The art of computer programming,
  Volume IFundamental algorithms

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Putting all together

• we introduce DLX (deluxe) architecture
• a simple load store instruction set
• design for pipeline efficiency, including a fixed
  instruction set encoding( we will discuss very
  soon)
• Efficiency as a compiler target

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DLX Roman letter for 560

• AMD 29K,DECstation 3100, HP850, IMB801, Intel
  i860, MIPS M/120A, MIPS M/1000, Motorola 88K,
  RiSC1, SGI 4D/60, Sparcstation-1, sun-4/110,
  Sun-4/260)/13560DLX

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why DLX

• DLX provides a good architectural model for study
• not only recent popularity of this type of
  machines
• easy architecture to understand

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We will discuss

• Registers for DLX
• Data type for DLX
• addressing mode for DLX data transfers
• DLX instruction format
• DLX operations
• Effectiveness of DLX
• Concluding Remarks

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Registers for DLX

• DLX has 32 32-bit general purpose registers(GPRs)
• R0, R31
• additionally there is a set of floating point
  registers (FPRs)--which can be used as 32 single
  precision (32 bit) registers or as even-odd pairs
  holding double precision values
• thus the 64-bit floating point registers are
  named F0, ,. F30

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• both single and double precision floating point
  operations are provided
• the value of R0 is zero -- we will see later how
  we can use this register to synthesize a variety
  of useful operations from a simple instruction
  set
• A few special registers can be transferred to and
  from the integer registers.
• Example the floating point status registers used
  to hold used to hold information about the result
  of floating point operations.
• FPR to GPR

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Data type for DLX

• data types are 8 bit, 16 bit half words, and 32
  bit words for integers data and 32 bit single
  precision and 64 bit double precision for FP
• The DLX operations work on 32 bit integers and 32
  or 64 bit floating point
• Bytes and half words are loaded into registers
  with either zero or the sign bit replicated to
  fill the 32 bit of the registers. Once loaded
  they are operated on with the 32-bit integer
  operation

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