Analyzing the Surface Roughness of Gate Dielectrics

1
Analyzing the Surface Roughness of Gate
Dielectrics
Abstract Nanotechnology is a multidisciplinary
field that deals with particles on the atomic
scale, generally between 1 and 100 nanometers in
size. This field is extremely promising due to
the difference in material properties between a
nanomaterial, and that same material in bulk
form. This study focused on determining the
surface roughness of three samples of Al2O3,
which were made in different processing
conditions, by comparing their texture statistics
to that of a control (cleaned silicon). The
samples were prepared by Jet Vapor Deposition
with the flow rate and carrier gas as variables
and imaged using the atomic force microscope
(AFM) in tapping mode. The AFM images were
processed in ImageJ and utilized the plug-in
Batch Texture which returned 16 texture
parameters. These parameters, as well as two
obtained directly from the AFM, were graphed
against those for the control substance to
determine which parameters best classify surface
roughness. The best parameters were found to be
RMS roughness and mean roughness, both of which
were obtained from the AFM. According to these
parameters, sample 2, which was prepared at a
flow rate of 300 sccm with carrier gases of Argon
and Nitrogen, was the smoothest of the three
samples.
Analysis The graphs below compare the average
values for each parameter. The parameters that
best represent surface texture would have the
control value as either the highest or lowest for
that factor, and the other samples should be
significantly different from the control.
Scrutinizing these graphs revealed that the best
factors were RMS roughness, mean roughness,
kurtosis, angular second moment (on both the 0
and 90 angles) and entropy (on both the 0 and
90 angles).
Sample Preparation The dielectric was
deposited onto the substrate by a process called
Jet Vapor Deposition (JVD). The system operates
using jets in a low vacuum (.14 torr) maintained
by mechanical pumps. The source metal is placed
in the throat of the nozzle, where it is
vaporized by a filament into a stream of carrier
gas. When the pressure within the nozzle reaches
a critical ratio (usually about 2), the gas
exiting the nozzle reaches supersonic speeds
where it is transported onto the substrate in a
uniform thickness of 50-60 ?.4 The source metal
used in this experiment was aluminum. The
carrier gas and flow rate varied by sample. After
JVD, all the samples were annealed with Nitrogen
at 900 C for 10 minutes.
Sample 3 Carrier gas Ar Flow 400 sccm
Sample 1 Carrier gas Ar N2 Flow 400 sccm
Sample 2 Carrier gas Ar N2 Flow 300 sccm
Atomic Force Microscope (AFM) After the samples
were prepared, they, as well as the control of a
flat piece of silicon cleaned with acetone, had
to be segmented (by a standard cleaving
technique) and mounted onto an AFM magnetic stub.
The completed slides were imaged using the atomic
force microscope in tapping mode. In this mode,
the cantilever (and tip) is oscillated above the
sample. Interatomic (Van Der Waals and Coulomb)
forces cause dampening as it approaches the
sample, which causes intermittent tapping between
the tip and sample. The image is created by
measuring the amplitude of those interactive
forces. Each sample was imaged in five to ten
locations at 15 nm above the sample, resulting in
a 1 micron by 1 micron scan area. This height
and scan size were experimentally determined to
yield the best quality images for all the
samples.
Introduction Integrated circuits, more commonly
known as chips, are semiconductor wafers that
are deposited with billions of transistors,
capacitors, diodes, and resistors. They are used
in all electronic devices from cell phones to
microprocessors to automobiles. In our
modern-day world, electronics are decreasing in
size, but increasing in importance. Moores Law
predicted that the number of transistors on an
integrated circuit will increase exponentially.
For the past forty years, we have been following
this prediction, with the number of transistors
on a chip doubling approximately every two years.
Increasing the capacity per area of circuitry in
an integrated circuit is generally very
desirable. As feature size decreases, cost and
power usage decrease and speed and overall
performance increase. Now, however, some
problems are being encountered on the nanometer
scale. The quest to make transistors
smaller is beginning to make them much less
efficient. This dilemma is described as
subthreshold leakage, which is when a current
flows between the source and drain of a MOSFET
when the applied voltage is less than the
threshold voltage. Subthreshold leakage is
occurring because the gate dielectric (or gate
oxide) in the transistor, which is supposed to
electrically isolate the transistor gate from the
channel where the current flows, is becoming too
thin. The material currently being used as the
gate dielectric is SiO2 and it measures only five
atoms thick. Because of this, electrons can
tunnel through the dielectric and enter the
channel when the transistor is supposed to be in
the off position. Unwanted direct tunneling
leakage current in a thin oxide is the most
critical limiting factor in conventional
transistor scaling. One approach for resolving
this problem includes replacing SiO2 with a
material with a higher permittivity constant (k).
The need for dielectrics with high-k
values can be easily explained with the equation
for capacitance, which is the efficiency of
moving charge
AFM Images of each sample
In order to determine which factors successfully
categorize surface roughness, another set of
graphs was created. . In the graphs below, the
percent difference between the control and the
various samples was used to better illustrate
which parameters could best distinguish surface
texture. From these graphs, the RMS roughness
and the mean roughness were found to be the best
factors for determining surface roughness. Both
of these factors were obtained directly from the
AFM. The next best factor was kurtosis, followed
by entropy, followed by angular second moment.
AFM at SCSU
AFM Diagram
Results Images taken in the AFM were saved
by date and sample name in the NanoScope format.
The raw images provided no useful information
until they were flattened using the microscopes
programming. The flatten command removes
unwanted features from scan lines by calculating
individual least-square fit polynomials and
subtracting them from each scan line. This
process removes artifacts that are caused by
specimen mounting (and should not impact true
surface effects). The AFM categorizes surface
texture by returning RMS roughness and mean
roughness values which were recorded for each
flattened image. All the pictures were exported
in TIFF format so they could be processed further
in ImageJ, a java based image processing program.
In ImageJ, each TIFF image was cropped so that
only the scan would be analyzed, and converted to
an 8 bit grayscale image.
In this equation, C is the capacitance, k e0 is
the permittivity of the dielectric times the
permittivity of free space, A is the area of the
capacitors plates, and d is the thickness of the
dielectric. Since k and d are inversely related,
if the dielectric had a higher k value, then it
could afford to be thicker to prevent
subthreshold leakage, and still have the same
amount of efficiency. The focus of this study
was to analyze the surface roughness of three
samples of Al2O3 that were prepared in different
processing conditions. The surface texture of
the dielectric has been found to predict electron
mobility, amount of current leakage, and defects
in other sample layers. Therefore, the ideal
gate dielectric should be as smooth as possible.
To classify the roughness of our samples,
different quantitative texture parameters were
collected and compared to a control.
Conclusion For the limited number of cases
evaluated in this study, it appears that
parameters obtained directly from the AFM are
better than any statistical parameters
investigated. These parameters of RMS roughness
and mean roughness had a minimum percent
difference from the control of 72.52 and 47.04
respectively. The other significant parameters
of kurtosis, entropy and angular second moment
had minimum percent differences of 29.52, 8.92
and 14.15 respectively. Using these factors to
classify the roughness of the three samples leads
to the deduction that sample 2 has the smoothest
surface, sample 1 is a little rougher, and sample
3 is the roughest by a considerable amount. This
means that the ideal processing condition for
this gate dielectric is at a flow rate of 400
sccm and with both Argon and Nitrogen as the
carrier gasses.
Once in the correct format, the images were
analyzed using a Batch Texture plug-in. This
method of image analysis was created by Thomas E.
Sadowski by adapting macroscopic texture
techniques to the microscopic scale. The plug-in
returned called upon the Roughness Calculations
plug-in to return the first order histogram
statistics of mean pixel value, standard
deviation of pixel value, skewness, and kurtosis,
and the Texture Analyzer plug-in to returned the
grayscale Cooccurrence texture statistics (as
defined in the Haralick paper10) of angular
second moment, contrast, correlation, inverse
different moment, and entropy.11 The texture
statistics from the Cooccurrence matrix were
collected in both the 0 and 90 directions.
After the Batch Texture plug-in finished
analyzing all the grayscale images, it created a
file called textureResults which contained all
the texture values for every image in the
directory. These 14 parameters, along with the 2
from the AFM (RMS roughness and mean roughness),
were organized in an Excel spreadsheet to be
analyzed.
Sponsors National Aeronautics and Space
Administration (NASA) NASA Goddard Space Flight
Center (GSFC) NASA Goddard Institute for Space
Studies (GISS) NASA New York City Research
Initiative (NYCRI) Southern Connecticut State
University (SCSU) Contributors Dr. John
DaPonte Dr. Christine Broadbridge Leah Mirabelle
Patrick Benjamin Bethany Niedzielski
References http//nobelprize.org/educational_game
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http//rsbweb.nih.gov/ij/ -imagej Ma, T.P.,
Making Silicon Nitride Film a Viable Gate
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Connecticut State University, May 2005.