A Unified Approach to Design Distributed Amplifiers

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A Unified Approach to Design Distributed
Amplifiers
Rasit Onur Topaloglu PhD. Student rtopalog_at_cse.ucs
d.edu
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Limitations with Classical Amplifiers

• High Gain-bandwidth product is the aim in
  amplifier design

• Gain-bandwidth product is proportional to
  transconductance over capacitance

G.BW ? gm/C

• Combining amplifiers in parallel does not help
  as it also increases the total C

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Tying Amplifier to Device Physics

• Input and output have capacitive impedances

D
G
Cgs
Cds
S

• These capacitances can be incorporated in or
  counted as capacitors in a transmission line

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Basic Transmission Line

• A low-pass transmission line can easily be
  constructed of inductors and capacitors

..
5
Principle of Distributed Amplification

• Couple two transmission lines by amplifiers

..
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Termination of Unwanted Waves

• There will be forward and backward propagating
  waves at nodes

RFout
..
RFin
..
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Exploitation of Amplifier Capacitances

• Input and output capacitances of an amplifier can
  be used to replace capacitors

..
drain line
RFout
..
RFin
gate line

• Even a single transistor amplifier satisfactory

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Design Considerations for Transmission Lines

• Each lines designed to have a cut-off frequency
  larger than targeted operation frequency of
  amplifier by a safe margin

fc1/(? LC)
Zo L/C
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m-derived Sections for a Better Matching

• LC sections (constant-k transmission lines)
  matched to load using an m-derived section to
  provide constant Z over a wider range

• m0.6 is identified as a practical rule of thumb
  value

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m-derived vs. Constant-k Low-pass T-section

• m1 corresponds to constant-k

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m-derived vs. Constant-k Line Z over Frequency

• m1 corresponds to constant-k

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Phase Matching of Lines

• Cgs4Cds for a transistor

• If L chosen to be constant, C matching required
  on gate and drain lines for a better amplifier
  response

• Either add additional C in parallel with drain to
  increase itgt provides higher BW

• Or add additional C in series with gate to reduce
  itgt provides higher gain

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Staggering to Avoid Gain Peak near Cut-off

• Staggering is introducing a deliberate mismatch
  between gate and drain lines to avoid a peak near
  line cut-off frequency

• Drain line cut-off chosen as 0.7 times gate line
  cut-off

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Number of Sections

• Increasing number of sections increases gain
  linearly as opposed to quadratic increase in
  cascade amplifiers

Ag1/4 x (Rg?2Cin2Zo)

• Line losses and parasitics prevent an infinite
  increase

nog1/2 x Ag

• Optimal number of stages can be explored
  analytically or by simulation

A monolithic GaAs 1-13GHz traveling wave
amplifier, Y. Ayasli, et. al.
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Design Example
SOI CMOS Traveling Wave Amplifier with NF below
3.8 dB from 0.1-40 GHz, F. Ellinger
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Design Example
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Design Example
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Design Example
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Design Example
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SOI CMOS Noise Figure and Gain
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PHEMT Noise Figure and Gain
Lossy Inductor Model Inductor Q assumed 20 _at_
1GHz with a parasitic series resistor of 10? and
Q being directly proportional to frequency
Technology Comparison SOI CMOS 90nm, 17mA,
2V Cgs0.06pF Cds0.015pF PHEMT 40mA,
2V Cgs0.27pF Cds0.030pF
Higher capacitance values makes possible to use
smaller inductors for same
cut-off frequency
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Design Considerations for PHEMT

• Cds used to decrease the high ratio difference
  between Cgs and Cds thereby obtaining a gain
  with less ripple.
• Compromising high frequency gain, a smoother
  response is obtained
• Usage of series Cgs would deteriorate low
  frequency response
• Same inductor value used for both gate and drain
  lines

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PHEMT GainNoise Optimization

• Goals are set for gain and noise

• Random optimization used

• Only inductor used for the optimization value
  thereby keeping system specific termination and
  source resistors intact

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PHEMT Optimization Results
After optimization
With some sacrifice in gain ripple, noise figure
has been significantly improved and circuit
operates up to 47GHz
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Usage of Transmission Lines
After optimization

• Using Richards transformation, inductors can be
  replaced by transmission lines.
• Choosing an electrical length of 45? and a
  reference cut-off frequency equal to the gate
  line, optimization gave a Zo of 30.6 and an
  operation range of up to 57 GHz for noise
  considerations

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Conclusions

• Broadband techniques will not be able to outdo
  distributed amplifiers

• Distributed amplifiers, an ancient field of
  study, will continue evolving as a good field to
  work in

• 60GHz low noise amplifiers for optical circuits
  are almost here

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Design Plan

• Given gain and bandwidth considerations,
• Identify pick fc and Zo for gate line to find Lg
  and

fc1/(? LC)
Zo L/C

• Using staggering with 0.7

Ld(1/0.7)Lg
Cd(1/0.7)Cg

• Find shunt capacitance to get Cd from device model

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Design Plan

• Identify device size using Cg

WL Cg/Cox

• Using staggering with 0.7

Ld(1/0.7)Lg
Cd(1/0.7)Cg

• Find shunt capacitance to get Cd from device model