COMP541 Combinational Logic - 2

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COMP541Combinational Logic - 2

• Montek Singh
• Jan 18, 2007

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Friday Labs

• No lab tomorrow start Jan 26
• Fairly fast PCs in lab
• To use your laptop, go to
• http//www.xilinx.com/ise/logic_design_prod/webpac
  k.htm
• Windows or Linux
• Dont install Modelsim see me

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Homework

• HW1 will be assigned Jan 23, due Jan 30
• Send via email or paper

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Topics

• More gates
• Simple Verilog
• Minterms and maxterms (again!)

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Exclusive OR

• Exclusive OR
• What lay people mean by or
• Symbol is ?
• Plus in a circle

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Parity Function

• Recall how parity works
• Ask class
• Write truth table for two input even parity
• What needs to be generated for parity bit?
• What function of two inputs gives you this?

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XOR Gives Odd Function

• As many inputs as necessary
• How do you get odd parity?
• Design even parity generator for 3-bit signal
• Perhaps make truth table and K-Map
• Draw with XOR, then sum-of-products w/ NAND gates
• How do you design a detector?
• How about a 7-bit ASCII character?

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Buffer

• No inversion
• No change, except in power or voltage
• Used to enable driving more inputs

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Others
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Tri-State

• Output w/ 3 states H, L, and Hi-Z
• High impedance
• Behaves like no output connection if in Hi-Z
  state
• Allows connecting multiple outputs

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Multiplexed with Hi-Z
Smoke

• Normal operation is blue area

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CMOS Transmission Gates

• Act like electronic switches

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XOR w/ Transmission Gate
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Schematic Diagrams

• Can you design a Pentium or a graphics chip that
  way?
• Well, yes, but diagrams are overly complex
• These days people represent the same thing with
  text (code)

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Hardware Description Languages

• Main ones are Verilog and VHDL
• Others Abel, SystemC, Handel
• Origins as testing languages
• To generate sets of input values
• Levels of use from very detailed to more abstract
  descriptions of hdw
• Think about C from assembly level description
  to very abstract HLL
• Today very basic use of Verilog

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Levels of Verilog

• Structural
• Dataflow
• Conditional
• Behavioral
• Look at first two today

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Example 1

• Output is 1 when input lt 011

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Structural Verilog

• Explicit description of gates and connections
• Textual form of schematic
• Specify netlist

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Example 1 in Structural Verilog

• module example_1(X,Y,Z,F)
• input X
• input Y
• input Z
• output F
• //wire X_n, Y_n, Z_n, f1, f2
• not
• g0(X_n, X),
• g1(Y_n, Y),
• g2(Z_n, Z)
• nand
• g3(f1, X_n, Y_n),
• g4(f2, X_n, Z_n),
• g5(F, f1, f2)
• endmodule

Can also be input X, Y, Z
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Slight Variation Gates not named

• module example_1_c(X,Y,Z,F)
• input X
• input Y
• input Z
• output F
• not(X_n, X)
• not(Y_n, Y)
• not(Z_n, Z)
• nand(f1, X_n, Y_n)
• nand(f2, X_n, Z_n)
• nand(F, f1, f2)
• endmodule

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Explanation

• Each of these gates is an instance
• Like object vs class
• In first example, they had names
• not
• g0(X_n, X),
• In second example, no name
• not(X_n, X)
• Later see why naming can be useful

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Gates

• Standard set of gates available
• and, or, not
• nand, nor
• xor, xnor
• buf

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Dataflow Description
module example_1_b(X,Y,Z,F) input X
input Y input Z output F assign F
(X Y) (X Z) endmodule

• Basically a logical expression
• No explicit gates

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Design from Specification

• So, now that we know how to implement, lets talk
  about how to specify
• Usually we can make up a truth table from specs
• Is there a mechanical way to come up with a
  function?
• Are there standard ways to structure the gates in
  the design?

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From Truth Table to Func

• Consider a truth table
• Can implement F by taking OR of all terms that
  are 1

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Lets Look at Standard Forms

• Not necessarily simplest F
• But its mechanical way to go from truth table to
  function
• Definitions
• Product terms AND ? ABZ
• Sum terms OR ? X A

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Definition Minterm

• Product term in which all variables appear once
  (complemented or not)

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Number of Minterms

• For n variables, there will be 2n minterms
• Like binary numbers from 0 to 2n-1
• In book, numbered same way (with decimal
  conversion)

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Maxterms

• Sum term in which all variables appear once
  (complemented or not)

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Minterm related to Maxterm

• Minterm and maxterm with same subscripts are
  complements
• Example

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Sum of Minterms

• OR all of the minterms of truth table for rows
  with a 1 output

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Sum of Products

• Simplifying sum-of-minterms can yield a sum of
  products
• Difference is each term need not have all
  variables
• ANDs and one OR

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Two-Level Implementation

• Sum of products has 2 levels of gates

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More Levels of Gates?

• Whats best?
• Hard to answer
• More gate delays (more on this later)
• But maybe we only have 2-input gates

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Complement of a Function

• Definition 1s 0s swapped in truth table
• Mechanical way to derive algebraic form
• Take the dual
• Recall Interchange AND and OR, and 1s 0s
• Complement each literal

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Complement of F

• Not surprisingly, just sum of the other minterms
• In this case
• m1 m3 m4 m6

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Product of Maxterms

• Recall that maxterm is true except for its own
  case
• So M1 is only false for 001

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Product of Maxterms

• Can express F as AND of all rows that should
  evaluate to 0

• or

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Product of Sums

• Result another standard form
• ORs followed by AND

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Read Do

• Chapter 3, Sections 1 3

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Next Week

• Software demo, and first lab
• Hierarchical Design
• How do we express something more complex in
  Verilog
• Implementation
• Brief look at logic families
• Packages
• Timing characteristics, delay
• Then look at storing data