Toward a general purpose computer II

1
Toward a general purpose computer II

• Example Game of Life

2
Problems in the previous implementation

• Similar instructions in different parts of the
  algorithm require different lines

Very large ROM
3
Example
tmp i1

• N N1

Target A B
4
Problems in the previous implementation

• All the variables of the algorithm are stored in
  registers.

1. Change in the algorithm will require change in
hardware 2. Registers are expansive. 3. There is
limited space.
5
Solution to 1 (and 2)

• Define more general instructions
• The algorithm will be a set of the general
  instructions.

6
List of instruction in game of life
Register no. 2

• 3 1 2
• 3 1 2
• 3 And(1,2)
• 3 OR(1,2)
• 3 Decode(1)
• 3 set on less 1,2
• 1 VAL

7
The set on less instruction

• 3 set on less 1,2
• 3 0000001 if 1 lt 2
• 3 0000000 otherwise.

8
ALU codes
9
Solution to 2

• Move the variables to the RAM

We will need instructions to load and store
registers in the RAM
10
Load and Store instructions

• Load addr,1 load address into 1
• Store addr , 1 store 1 into addr

11
Instruction control

• Goto the next instruction
• j Addr
• Jump to instruction in address addr

12
Control the PC branching
1
2
3
4
13
Control the PC branching

• PC PC1
• Check xxx happenedIf it didnt PC 4
• IR ?PC

1
2
3
4
14
PC control

• Jne 1,2,Addr
• If 1 ? 2 ? Goto Addr
• Je 1,2,Addr
• If 1 2 ? Goto Addr

15
The instructions in the system
Arithmetic/Logic operations
Memory related operations
Control operations

• 3 1 2
• 3 1 2
• 3 And(1,2)
• 3 OR(1,2)
• 3 Decode(1)
• 3 set-on- less(1,2)
• 1 VAL

• j Addr
• Jne 1,2,Addr
• Je 1,2,Addr

• Load addr,1
• Store addr,1

Instruction
16
Assumptions

• We have 16 registers 126
• (0 is always zero).
• The RAM has 65536 entries of 16bits
• (16bit address)
• The program ROM has 65536 entriesof 32bits each.
  

17
The structure of instructionsArithmetic logic
Total 16 registers
0-4First 5 bits reserved
5-8
9-12
13-16
18
The structure of instructions1 VAL
0-4First 5 bits reserved
5-8
9-24
19
The structure of instructionsMemory instruction
load/store addr,1
0-4
5-8
9-24
20
The structure of instructionsControl instructions
j/jne/je 1,2,Addr
0-4
5-8
9-12
13-28
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Note about the control instructions

• In the j instruction we ignore the
• first and second fields.

22
The components of the circuitThe ALU
Operand A
Operand B
ALU
Operation Code
Is zero(1 bit)
Result
23
The components of the circuitThe Registers
Registers
Data 1 Address
Data 1
Data 2 Address
Data 2
WriteAddress
Write Data
Write
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The components of the circuitThe RAM
Read
Note 1 The RAM is the one you saw in class
without the MAR and MBR Note 2 The RAM is
implemented with Latches!
RAM
Read Address
Data 1
WriteAddress
Write Data
Write
25
The components of the circuitThe PC and the
program

• PC holds the next address
• IR - holds the current instruction

Program ROM
IR
PC
Write
Write
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A note before implementation

• Several time cycles were lost because not all
  instructions have the same number of steps.

Solution Use a counter for the
micro-instructions. CAR
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The components of the circuitCAR, example with
arithmetic instruction
Goto the next instruction

• CAR 0 IR?PC, PCPC1, CARCAR
• CAR 1 Perform the code
• CAR 0

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The components of the circuitCAR, example with
jne 1,2,Addr
Goto the next instruction

• CAR 0 IR?PC, PCPC1, CARCAR
• CAR 1 1-2, if not zero PC?Addr CAR 0

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The components of the circuitCAR, example with
arithmetic instruction
Goto the next instruction

• CAR 0 IR?PC, PCPC1, CARCAR
• CAR 1 Perform the code

For efficiency, we will NOT use the ALU here.
30
The CAR circuit
1
CAR
Adder
C1
MUX
000
31
Program ROM
IR
PC
3
BITS 13-28
BITS 5-8
16Registers
BITS 9-12
1
BITS 5-8
5
2
BITS 13-16
4
BITS 9-24
BITS 5-8
RAM
1
ALU
BITS 9-24
32
Mirco-instructions
CAR
Program ROM
IR
PC
BITS 0-4
3
All the control in the system
BITS 13-28
BITS 5-8
16Registers
BITS 9-12
0
1
1
BITS 5-8
5
1
0
1
2
BITS 13-16
0
4
BITS 9-24
2
BITS 5-8
RAM
1
1
ALU
0
BITS 9-24
33
Mux3
CAR
Program ROM
IR
PC
3
CAR control
IRload
PCload
Mux2
Mux5
16Registers
1
5
Read
2
Mux4
4
RAM
ALUop
1
ALU
Write
Mux1
Write
34
The micro-instruction ROM
35
The micro-instruction ROMExample
CAR 0 IR?PC, PCPC1, CARCAR CAR
1 321 CAR 0
36
The micro-instruction ROMExample
We dont care about these
CAR 0 IR?PC, PCPC1, CARCAR CAR
1 321 CAR 0
The meaning is Put in PC the result Of PC1
37
The micro-instruction ROMExample
CAR 0 IR?PC, PCPC1, CARCAR CAR
1 321 CAR 0
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In addition

• In order to implement the jne instruction we need
  a conditional write on the PC.
• The essence is in here

39
Addition to the ROM
1-bit flags that are used in the jne,je
40
Mirco-instructions
Program ROM
IR
PC
PC write
Branch equal
Branch not equal
ALU
Zero status bit
41
The program ROM
Instruction type 00
Instruction sub type
Reg3
Reg1
Reg2
42
Saving more space

• The fetch is divided into 2 cycles
• Fetch instruction
• Goto Right instruction

The ROM will depend on the CAR alone
43
CAR

• Arithmetic 1 micro instruction
• Load 2 micro instructions
• Store 2 micro instructions

44
CAR the instruction-CAR table
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CAR Order of execution
Assume we are executing the instruction Load
46
CAR Order of execution
Assume we are executing the instruction Load
47
CAR Order of execution
Assume we are executing the instruction Load
48
Implementation of the Goto in the CAR circuit
1
CAR
Adder
C1C2
MUX
000
Instruction CAR table
The Instruction
49
BITS 0-4
Mirco-instructions
CAR
Program ROM
IR
PC
3
All the control in the system
BITS 13-28
BITS 5-8
16Registers
BITS 9-12
0
1
1
BITS 5-8
5
1
0
1
2
BITS 13-16
0
4
BITS 9-24
2
BITS 5-8
RAM
1
1
ALU
0
BITS 9-24
50
The micro-instruction ROM
The micro instruction ROM depends on the CAR only
now.