FPGA CAD

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FPGA CAD
10-MAR-2003
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Content

• FPGA CAD design flow
• Placement
• Routing.
• (top ten hottest VLSI CAD problems)

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FPGA Design Flow

• Designing with FPGAs is much like the ASICs
  technology.
• The Computer Aided Design (CAD) software provided
  by the FPGA vendor or third part is used to
  convert the given digital circuit (schematic or a
  high level description in VHDL or Verilog) into a
  stream of bits, which is then used to download to
  the FPGA.

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CAD Tools
MaxPlus
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A Typical FPGA CAD Flow
Design Entry
Logic Optimization
Synthesis
Mapping to k-LUT
Packing LUTs to CLBs
Placement
Routing
Download to FPGA
Simulation
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Placement Find home for CLBs.
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Problem define

• Assign position(X, Y) to modules
• Placement to minimize
• total wirelength
• critical path wirelength
• a combination of them.
• Estimated model
• Circuit quality is determined by placement
  routing
• Routing is a NP-hard problem.
• NP-hard problem. (n!)
• Time is a big issue.
• Quality and time tradeoff.

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circuit before placement
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circuit after placement
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Heuristic method

• Constructive methods
• Partitioning method min-cut
• Clustering.
• Iterative improvement
• Begin with a random or constructive placement
• Iterate to improve it
• Force directed method
• Simulated annealing.
• Other method
• Genetic algorithm

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Min-Cut
Minimize cuts during partition
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Force directed method

• Classical mechanics
• Using Hookes law
• Force vector computed on each module
  corresponding to all nets connections
• Solve a set of non-linear differential equations.

force
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Simulated annealing

• Generates best results (industry standard)
• Run time is a issue.
• Model a physical annealing process.
• VPR placer (placement tools available to us,
  developed in UoT).

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Physical Annealing

• Take a metal and heat to high temperature until
  liquidized
• Allow it to cool slowly, metal is annealed to a
  low temperature
• Atoms in the metal are at transfer from high
  energy states to low energy states
• Can accept bad moves to get global minima.
• Avoid getting trapped in local minima.

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Comparison
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Routing-Find the path

• Maze routing
• Pathfinder.

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Routing Resource
Connection Block
Switch Block
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Typical Connection
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Maze router
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Pathfinder router

• Based on maze router
• Shows very high quality results
• Negotiation-based router
• Each net negotiates the use of shared resources
  with other nets until none of the resources are
  shared
• Extra weights are added to shared resources.
• VPR router

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Comparison
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Questions
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Placement Routing
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Design Entry

• The description of a logic circuit can be entered
  by using a schematic capture program
• VHDL and Verilog interpreter.

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Synthesis

• A circuit description such as VHDL, is first
  converted to a netlist of basic gates. This
  process called synthesis.

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Logic Optimization

• technology independent
• Improve circuit, while keep functionality
  correct

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Mapping to LUTs

• The gates then are mapped into k-input lookup
  tables (LUT). (most basic brick of FPGA)
• Chortle. (available to academic, developed in
  UoT)

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Packing LUTs into CLBs

• Configurable Logic Block (CLB)
• Grouping the LUTs into CLBs
• Simi liar to circuit clustering.
• Vpack. (available to academic, developed in UoT)

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Placement

• Placement is to determining the physical location
  of each CLBs on the FPGA

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Routing

• Realize connections among the CLBs by selecting
  routing resource.
• wire segments and
• routing switches.

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Simulation

• After placement and routing, the implemented
  design is simulated to ensure its functioning and
  to verify the timing issues.
• Design errors can be found and corrected at this
  stage.

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Download bits file to FPGA

• Once all the necessary steps are completed for
  implementing the design, the CAD system can
  download the result to the programming unit that
  is used to configure the FPGA
• After this stage, the programmable device is
  configured and ready for use.