SystemVerilog

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SystemVerilog
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History

• Enhancement of Verilog
• 2002 accellera publishes SystemVerilog 3.0
• 2004 - accellera publishes SystemVerilog 3.1a
• 2005 IEEE standardizes SystemVerilog

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Whats in it

• Verilog
• Modeling
• New constructs
• Synthesizable
• Verification
• Testbench automation
• Assertions

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SV for Modeling

• Verilog
• Interfaces
• Data types 2 and 4 levels, int, shortint,
  longint, byte, logic, typedef
• 2-state modeling
• Flow control mechanisms Break, continue,
  return,
• Casting
• And much more ...

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SV for Verification

• Generation Constrained random generation
• Check Assertions
• Coverage
• Semaphores
• Test program blocks
• Classes
• Inheritance
• And much more

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Constrained Random Generation

• Within class
• Fields should be declared as random
• class packet
• randc bit70 addr
• rand bit70 data
• constraint legal_pkt
• addr 2
• endclass

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Interface

• Separate communication from functionality
• A bundle of wires that simplifies hierarchical
  connections
• The block uses an interface

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Available Tools

• Training
• Consulting
• Simulators
• SVA packages
• Methodology
• Synopsis, Mentor, Cadence
• Everybody has something

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So?

• Good new capabilities
• Modeling and verification in same language
• Apparently all verification services

• Suitable for designers?
• Synthesizable
• Complicated to learn
• Immature tools
• Immature methodology
• No experience