8Bit Arithmetic Logic Unit ALU

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8-Bit Arithmetic Logic Unit (ALU)

• Jeffrey Huang, Ying Ji
• Chongmei Zhang, Xiaoyang Zhang
• Advisor Dr. David Parent
• San Jose State University
• May 8, 2006

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Agenda

• Abstract
• Introduction
• Project Details
• Schematics, NC Verilog
• Hand Calculations
• CMOS/Complex Logic Gate Sizes
• Layout, DRC, Extraction, LVS
• Worst-Case Analysis
• Simulation Results
• Results
• Cost Analysis, Lessons Learned
• Conclusions

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Abstract

• Our team successfully designed an 8-bit ALU using
  
• two 4-bit CLA stages.
• ALU performs 8 arithmetic operations and 4 logic
  functions.
• Designed circuit was simulated and verified in
  schematic and layout.
• We used the AMI06 process technology in our
  design.
• Design meets 200 MHz operation speed
  specification.
• Circuit power consumption is 29.9 mW and has an
  area of 474.2 µm x 368.7 µm.

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Introduction

• We chose the Arithmetic Logic Unit as our design
  project because of its importance to the
  execution unit of a computers CPU.
• Our 8-bit ALU design is based on the 74LS181
  component.
• Arithmetic/Logic Operation controlled by four
  input lines S1, S2, M, and Cn.
• Our specification is to design for an operation
  speed of 200 MHz or faster.

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Project Details8-Bit ALU Logic Schematic
Logic gate schematic of 8-bit ALU showing
input/outputs.
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ALU Functions/Operations
ALU performs four logic functions and eight
arithmetic operations depending on the inputs
S3, S1, M, and Cn.
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NC-Verilog Simulation
NC-Verilog output simulation is shown for 4-bit
case for easier waveform readability.
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Worst-Case Vector Path
A3 set high and B3 toggled to produce a
carry-out from the first 4-bit stage into the
second.
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Hand Calculations for Size Delay

• Above are the design equations used in our hand
  calculations.
• We used a spreadsheet for quick accurate
  calculations.

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Transistor Sizes Delay Times
Our design goal was minimum width with symmetric
propagation time.
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D Flip-Flop Size Delay Time

• Table of transistor sizes used in our Mux-Based
  DFF.
• Design goal was to allocate 1 ns to the DFF.

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8-Bit ALU Layout
The overall layout of our ALU circuit using the
AMI06 process.
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ALU Block Layout
The ALU layout with the cell outlines shown.
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DRC Extraction Results

• Layout successfully passes DRC.
• Parasitic capacitances are extracted that will
  be used to compare
• if layout and schematic are electrically
  equivalent.

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LVS
Output file confirms LVS check is successful!
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Simulation Results
Simulation results for various test vectors.
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Worst-Case SPICE Simulation
Worst-case delay of analog_extracted circuit
3.98 ns
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Results

• 8-bit ALU performs eight arithmetic
  operations and four logic operations
• Operation speed 200 MHz
• Worst-Case Delay 3.98 ns
• Power 29.9 mW
• Area 474.2 µm x 368.7 µm

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Cost Analysis Project Design Time
Total project from start to finish was
approximately 5 weeks.
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Lessons Learned

• Very Important Lesson Time Management
• How to achieve symmetric propagation.
• Knowing where to use buffers.
• Paying attention to fan-in and fan-out.
• Using cell-based design simplifies layout.

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Conclusions

• The Arithmetic Logic Unit is an important part of
  computer CPUs. We learned how to produce
  different arithmetic operations and logic
  functions by using various select singles for a
  single circuit.
• Actual operation speed of designed ALU is faster
  than specification.
• Low power consumption and small area.
• Designed ALU was 8-bit, four bits more than
  previous projects.
• Preparation of an overall stick diagram of the
  entire circuit allowed quick, efficient
  organization of our layout.
• Great teamwork helped us achieve our project
  goal!

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Acknowledgements

• Thanks to Dr. David Parent for providing project
  guidance and very helpful tutorials.
• Thanks to Cadence Design Systems for the VLSI
  lab.
• Thanks to our families for putting up with us.
• Thanks to our colleagues in the lab.