Circuit and Logic simulators

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Circuit and Logic simulators

• -Ramakrishnan V
• VLSI Circuits and Systems Group,

2
Spice Pseudo-Code

• Source Z.Q.Zhang et al. Convergence Problems in
  Spice
• NR-Iteration Newton Raphson

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Spice operation

• Formulation of non-linear First-order
  differential equations representing the behaviour
  of the interconnected set of devices in the
  circuit
• Replacement of Time derivatives in the
  differential equations with difference
  approximations (generating time-independent set
  of non-linear equations).
• Solve the non-linear equations at each
  discretised time by Newton-Raphson method, which
  approximates them with a linear set of equations
  based on initial estimate of the solution
• Refine the solution to adequate precision
  (RELTOL, ABSTOL, VNTOL).

Source K.G.Nichols et al, Overview of SPICE like
circuit-sim algorithms, IEE 1994
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Spice operation (contd..)
Initial estimate plays a major role in convergence
Source K.G.Nichols et al, Overview of SPICE like
circuit-sim algorithms, IEE 1994
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Newton-Raphson Method

• The Newton-Raphson method uses an iterative
  process to approach one root of a function. The
  specific root that the process locates depends on
  the initial, arbitrarily chosen x-value.
• The term f(x)/f'(x) represents a value of dx.
• f(x) x2-4.

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Trapezoidal Rule

• The trapezoidal rule is a method for
  approximating a definite integral by evaluating
  the integrand at finitely many points. The formal
  rule is given by
• where

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Newton-Raphson Method (contd..)
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Event Simulator Operation
Source Shankars VHDL course foils
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Event Simulator Operation (contd)
Source Shankars VHDL course foils
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Cycle Vs Event Simulator

• Cycle based Simulator Cycle simulation does not
  simulate detailed circuit timing, but instead
  computes the steady state response of a circuit
  at each clock cycle. The user cannot see the
  glitch behavior of signals between clock cycles.
  Instead the user observes circuit signals once
  per clock cycle. Cycle based simulators work with
  only synchronous designs.
• Event based Simulation based on events in
  logic, which means, when ever there is change in
  a input event, the output is evaluated. This
  makes the simulation very slow compared to Cycle
  based simulators.

A cycle based simulator will evaluate B, C, D and
E only at each cycle. In the case of event based
simulator, B, C, D and E are evaluated not only
at clock cycle, but also when any of the events
at the input of gates and flip-flops occurs.
Source www.asic-world.com
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Agilent ADS and VHDL-AMS

• Agilent ADS Conventional Finite Element Method
  (Yet to read on this)
• VHDL-AMS Spice like (uses analog models along
  with digital logic simulation using Scirocco).

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Mixed Simulation in Powermill

• Simulation speed can be varied in Powermill at
  the cost of accuracy of the simulation. So it can
  operate in both extreme simulation modes even at
  RTL level Spice like precision / digital logic
  simulation.
• (Not analogous to Spice/IRSIM)
• Inputs are verilog/VHDL gate level netlist, spice
  models for each of the leaf cells, spice
  macromodels for each analog block(if any) and
  technology files.

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Nanosim-VCS

• Nanosim-VCS --- Capable of doing spice/RTL mixed
  simulation.
• Define Signal value conversions
• Logic 0 and 1 to analog voltages

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Some good papers

• PLL Modelling in a cycle simulation Environment
  (Two cycle simulators working in tandem with a
  handshaking algorithm) 1999.
• Issues Still a slow simulator
• http//www.research.ibm.com/journal/rd/435/vanhub
  en.pdf
• - Verification of Radio-Frequency
  Transceivers     http//www.mentor.com/techpapers
  /fulfillment/upload/mentorpaper_1199.pdf
•  Modeling of Timing Jitter in Oscillators David
  Lee (Mentor Graphics-2001)
•      http//www.mentor.com/techpapers/fulfillment/
  upload/mentorpaper_3544.pdf

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Time domain Model of PLL
Source Bogdans Slides on PLL Modeling