Hall D Electronics

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Hall D Electronics

Elke-Caroline Aschenauer
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Channel Counts
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Needed Electronics

• 250 MHz ADC (16ch) 387 modules 250/ch
• 100 MHz ADC (72ch) 175 modules 53/ch
• TDC 62ps (32ch) 89 modules
  103/ch
• TDC 125ps (64ch) 36 modules
  52/ch
• Disc/CFD (16ch) 164/11 modules
  150/360ch
• Splitters (16ch) 164 modules
• Energy Sum Modules 30 modules
  3000/module
• Clock Distribution 60 modules
  3000/module
• in addition preamp boards for chambers, boards
  for SiPMTs,
• HV-distribution boards Chambers and SiPMTs

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Assumptions and Reminders

• Detector ready for data taking after
  construction
• We have to pay for project specific jobs
• We have to pay for the modules
• Hall D has nothing existing on DAQ, Trigger or
• slow-control/monitoring software
• run with a trigger rate of 250 kHz
• all the electronics has to be pipe lined
• clock distribution precision lt 10 ps
• Want min 40 MeV Energy deposition for the BCAL
• gain fluctuations
• calorimeters go into 1st level trigger (trigger
  bias)
• want 60 ps TOF resolution

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WBS 1.5.3 Hall D

• DAQ
• single biggest procurement cpu boards 288k
• Raid disks computers 80k 83k
• Online Computing
• manpower to develop readout and monitoring
  software
• Offline Computing
• manpower to develop software needed to verify
  detector is operational (e.g., reconstruct cosmic)

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WBS 1.5.4 Hall D

• FADC
• biggest procurement 387 modules of 250MHz-FADC
  (16ch / mod) ? 4020 module
• 175 100MHz-FADC modules (72ch / mod) ? 3816 k
• TDC
• 89 modules of F1-TDC (62 ps with 32ch / mod.)
  3300 / mod.
• 36 modules of F1-TDC (125 ps with 64ch / mod. )
  3300 / mod.
• labor testing, calibration, integration in DAQ,
  clock distribution of all the system
• Logic / HV
• 1350 HV channels (280 /ch.)
• 164 discriminators (16ch) 2400 / mod.
• 11 CFDs (16ch) 5760 / mod.

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Testing/Manpower Philosophy

• Modules come in a very raw version
• no front panels, no connectors, no software
• test individual modules and crate assemblies
• develop test stand
• base it on CODA to allow to debug module drivers
• test linearity / gain of FADC calibrate
  Disc/CFD TDC
• test interplay FADC, Energy-Sum and VXS
  backplane
• develop gain correction data-base for FADC
• rate dependence of cross talk
• verify/test clock distribution is really below
  10ps
• long term / temperature stability
• specific example
• timing measurement for 100MHz FADC for CDC
  (lt2ns)
• test channel by channel with high frequency clock
  and input signal
• might need iteration on shaping part of the board
  to achieve negligible resolution from the FADC to
  the t-resolution

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Former Experience

• CLAS
• all TDCs and ADCs have been tested and calibrated
  channel by channel
• TDC took 24 hour / module
• HALL-D 1000 modules testing takes 5 years
• HERMES
• RICH photon detector
• tested 4000 PMTs with their individual
  electronics channel (PCOS) to determine noise and
  gain
• factor 2 less noise than needed took less than
  one month to get performance for physics
• Recoil Detector
• SciFi 5000 channels each individual GasiPlex
  channel was calibrated
• Silicon 8000 channles each individual ADC
  channels was calibrated

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Work for the FADC

• 100MHz FADC used for CDC and FDC
• 250MHz FADC used for CALOs, TOF, ....

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Work on TDC

• used for TOF (6), BCal (72), FDC (36)
• includes also all the work on the discriminators
• includes also all the work on the clock
  distribution

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Clock Distribution Work
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Work on Trigger
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Crate and Rack Layout
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Crate and Rack Layout