Chapter 4' Combinational logic

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Chapter 4. Combinational logic

• Logic circuits for digital system
• Combinational
• Sequential

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Combinational circuits

• Outputs are determined from the present inputs
• Consist of input/output variables and logic gates

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Analysis procedure

• To determine the function of circuit
• Analysis procedure
• Make sure the circuit is combinational or
  sequential
• Obtain the output Boolean functions or the truth
  table
• Boolean function
• Label all gate outputs
• Make output functions at each level
• Substitute final outputs to input variables
• Truth table
• Put the input variables to binary numbers
• Determine the output value at each gate
• Obtain truth table

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F2ABACBC
F1ABC(ABC)(ABACBC) ABC (ABC)
(AB)(AC) (BC) ABC(ABC)
(ABACBCBC) ABCABCABCABC
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Design procedure

• Determine the required number of input and output
  from specification
• Assign a letter symbol to each input/output
• Derive the truth table
• Obtain the simplified Boolean functions
• Draw the logic diagram and verify design
  correctness

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Code converter design example BCD to excess-3
code

• 1. Determine inputs/outputs
• Inputs A, B, C, D (00001001)
• Outputs W, X, Y, Z (00111100)
• 2. Derive truth table

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• 3. Obtain simplified Boolean functions

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• 4. Draw the logic diagram

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Half Adder

• performs the addition of 2-bits (xy)
• Input X(augend), Y(addend)
• Output S(sum), C(carry)

Sxy'x'y Cxy
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Half adder
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Full adder

• performs the addition of 3-bits (xyz)
• Input X, Y(2 significant bits), Z(1 carry bit)
• Output S(sum), C(carry)

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Full adder
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Binary adder

• Sum of two n-bit binary numbers
• 4-bit adder
• A1011, B0011

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Carry propagation

• All carry is a function of Pi,Gi and C0
• PiAi?Bi
• GiAiBi
• SiPi ?Ci
• Ci1GiPiCi

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Carry lookahead generator

• PiAi?Bi
• GiAiBi
• SiPi ?Ci
• Ci1GiPiCi

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4-bit adder with carry lookahead

• PiAi?Bi
• GiAiBi
• SiPi ?Ci
• Ci1GiPiCi

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Binary subtractor

• A - B A (2complement of B)
• M0 adder(B?0B),
• M1 subtractor(B?1B C01),

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Overflow

• Sum of n digit number occupies n1digit
• Occurs when two numbers are same sign
• examples of overflow

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Decimal adder BCD Adder

• CKZ8Z4Z8Z2

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BCD Adder

• Carry arise if output 10101111
• CKZ8Z4Z8Z2

1010 1011
1100 1101 1110 1111
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Binary multiplier

• Multiplication of two bits ? AND
• 2bits x 2bits 4bits (max)

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Binary multiplier

• K-bits x J-bits
• (K x J) AND gates,
• (J-1) K-bit adder needed
• B3B2B1B0
• x A2A1A0

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Magnitude comparator

• AA3A2A1A0
• BB3B2B1B0
• xiAiBiAiBi, i0,1,2,3
• (AB) x3x2x1x0
• (AgtB)A3B3'x3A2B2'
• x3x2A1B1'x3x2x1A0B0'
• (AltB)A3'B3x3A2'B2
• x3x2A1'B1x3x2x1A0'B0

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Decoders

• Generate the 2n(or less) minterms of n input
  variables
• E.g. 3 to 8 line decoder

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2 to 4 line decoder with Enable(E) input
complemented form more economical
1-to-4-line demultiplexer
Demultiplexer receives information from a single
line and directs it to one of
2n possible output lines
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Decoders with enable inputs can be connected
together to form a larger decoder circuit

• 4x16 decoder by two 3x8 decoders

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Decoders Combinational logic implementation

• Any combinational circuit can be implemented with
  line decoder and OR gates
• Eg full adder

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Encoders

• Inverse operation of a decoder
• Generate n outputs of 2n input values
• E.g.) octal to binary encoder

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Priority encoder

• Ambiguity 1 two or more inputs equal to 1 at the
  same time
• Ambiguity 2 all inputs are 0 D0 is 1

0
0
0
0
V valid bit indicator D3 the highest priority
X D2 D3 Y D3 D1D2 V D0 D1 D2
D3
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Implementation of 4-bit priority encoder

• X D2 D3
• y D3 D1D2
• V D0 D1 D2 D3

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Multiplexers data selectors

• Select a binary information from many input lines
• 2n input lines have n selection lines
• 2-to-1-Line Multiplexer

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4 to 1 line multiplexer
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Quadruple 2-to-1 line multiplexer
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Boolean function implementation

• The minterms of a function are generated in a MUX
  by the circuit associated with the selection
  inputs.
• n input variables, n-1 selection input
• Eg. F(x,y,z) ?(1,2,6,7)

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Implementing any Boolean Function of n variables
with a MUX with n-1 selection inputs and 2n-1
data inputs

• F(A,B,C,D) ?(1,3,4,11,12,13,14,15)

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Three-state gates

• Logic 1, 0 and high-impedance
• High-impedance behaves like an open circuit the
  output appears to be disconnected and the circuit
  has no logic significance
• A multiplexer can be constructed with
  three-state gates

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The Construction of MUX with three-state buffers