Serial Interfacing

1
Serial Interfacing

• Serial Data Transfer used by keyboards,
  plotters, modems and other peripherals with low
  data transfer rates (low bandwidth)
• 2 Types
• Asynchronous CPU and device are not using a
  common time reference - no common
  clock/timing signal
• - special bit patterns indicate begin/end
• - slower than synchronous
• Synchronous common time reference used
• - timing controlled
• - synchronization pulses related to a
  clock are sent/received
• - faster than asynchronous

2
Asynchronous Frame
10 bits 7E1 (7 data bits, even parity, 1 stop bit)
D0
D1
D2
D3
D4
D5
D6
P
D0
D1
ST
ST





10 bits 8N1 (8 data bits, no parity, 1 stop bit)
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
ST
ST





Mark A Constant Logic-1 Denoted by
Space A Constant Logic-0
Standard is for Serial Line to CONSTANTLY be
Driven to a MARK While Inactive
ST start bit 1 ASCII char. 7 bitsD0
LSB (e.g. DEL 7fh higher is PC
specific) D6(D7) MSB Typical is 10 bits for
asynchronous transfer P parity bit Serial
data with even/odd parity - stop bit a mark
Serial data receiver starts processing when 1)
high to low is sensed (start bit detection) 2)
following (7 or 8) bits represent a character 3)
parity bit for error detection 4) stop bit is
detected (a mark)
3
Frame Example
10 bits 7E1
0
1
1
0
0
1
1
0
1
1
1
1
1
0
- stop bit a mark
ST start bit
66h f ASCII Character
P even parity bit
When receiver sees a start bit (high to low
transition) 1) Local timer starts 2) Each bit
sampled at midpoint in time ( clock
tolerance) 3) Maximum tolerance is ½ of 1 bit
time interval over 10 intervals (½)/10 5
4
Electrical Parameters (asynchronous)
T0
0
1
?
?
ST
D0
?
Pulse width of 1 bit
T0 Start time for receiver clock Why is T0
less than ? ?
ANSWER Circuit delay for falling edge detection
circuit
V

• Voltage levels for 0, 1
• Typically NOT TTL levels
• Negative logic normally

1
time
?
-V
5
Baseband Signaling Speeds
6
Baud Rate vs Bits Per Second

• Baud rate is the rate at which signaling events
  are sent
• Data rate (bits per second, bps) is number of
  bits transferred per second (any type of bits,
  whether data or overhead bits)
• If only a single bit (1 or 0, either of two
  levels) is sent for each signaling event, then
  baud rate data rate (bps)
• However, could use a signaling protocol that
  transfers multiple bits per signaling event
• i.e., use 4 different voltage levels, send two
  bits of data per signaling event (00 -15v, 01
  -5v, 105v, 11 5v).
• In this case, bit rate will be double the baud
  rate
• The effective data rate is the rate at which data
  is transferred, minus the framing overhead bits
  (i.e., start, stop, parity bits).

7
Serial Port is 1-bit Parallel Port
LSB of Data Bus
out 0, al in al, 0
8
Serial Port Enable Signals
out 0, al
in al, 0
9
Recovering/Generating Serial Data- Timing Loop-
10
AL/CF Content During Timing Loop(assume A5h is
to be serially transmitted)
AL
CF
AL
CF
1
F4h
rcr
X
A5h
proc entry
1
F4h
stc
0
A5h
clc
0
FAh
rcr
1
4Ah
rcl
1
FAh
stc
0
A5h
rcr
0
FDh
rcr
1
A5h
stc
1
FDh
stc
1
D2h
rcr
1
FEh
rcr
1
D2h
stc
1
FEh
stc
0
E9h
rcr
0
FFh
rcr
1
E9h
stc
1
FFh
stc
11
AL/CF Content During Timing Loop(CONTINUED)
AL
CF
1
FFh
rcr
1
FFh
stc
1
FFh
rcr
1
FFh
stc
1
FFh
return from procedure
12
Synchronization of Serial Data

• Rx and Tx clocks may differ slightly in period
• Sampling is done at middle of bit time interval
• Can result in accumulation of error over 10-bit
  time interval
• Timing is reset at beginning of frame (Start
  bit)
• - Self-Synchronizing (after each character)

Proper data rate Too fast Too slow
13
Synchronous Serial Data

• No start/stop bits
• Data (and parity maybe) only

D0
D1
D2
D3
D4
D5
D6
D7
P
D0
D1
Advantage Faster (since no start/stop
bits) Disadvantage Clock must be transmitted
with data Initially a sync-frame is sent
followed by a block of data (which can be many
characters)
14
Universal Asyn. Receiver/TransmitterUART

• Special circuit that relieves processor from
  executing timing loops
• UART Characteristics
• Appears as a Parallel I/O Port to the x86
• Contains both Rx and Tx circuits
• Contains status registers (BUSY/READY and ERROR
  conditions)
• Types of errors UART can detect - Framing
  error - Invalid start bit received
• - Parity error - Single bit data error
  detected
• - Overrrun - Stop bit not found
• Most UARTs use a dedicated 16x clock signal
• - 1200 bps ? 19.2 kHz clock signal
• - Each bit divided into 16 time slices
• Rx circuit converts Serial to Parallel Tx
  converts Parallel to Serial
• - Combination PISO/SIPO registers

15
Register Types

• PIPO - Parallel Input Parallel Output
• SIPO - Serial Input Parallel Output
• PISO - Parallel Input Serial Output
• SISO - Serial Input Serial Output

16
PC16550D UART

• Transmit Functionality
• Receives 1 byte from processor
• Converts to serial form (PISO register)
• Adds start, stop and parity bits
• Clocks data out serially (Possible rates are
  0-256 kbps)
• Receive Functionality
• Receives serial frame from device
• Converts to parallel form (SIPO register)
• Checks for errors (framing, parity, overrun)
• Stores received byte for processor access
• Supported I/O control schemes
• Polling (parallel)
• Interrupts
• DMA
• Successor of the NS8250/8251 and 16540
• Need 1 16550 per Serial Port (typically 2 per PC
  since COM1 and COM2)
• NPC16552D is Single Package Device Containing
  Equivalent of 2 16550s

17
PC16550D UARTBlock Diagram
18
PC Interface
19
EIA RS-232 Serial Interface Standard

• EIA Electronic Industry Associates
• First RS-232 Standard in 1969 for
• DTE to DCE
• Initially Assumed Phone Lines used with Modems
  at Each End
• Latest is EIA232E in 1991 (no longer RS, but
  everyone still calls it that)

Data Terminal Equipment DTE
Data Terminal Equipment DTE
Data Terminal Equipment DTE
Data Terminal Equipment DTE
232
232
Phone Line
20
Basic 232 Specifications

• Maximum Data Rate 19,200 bps
• Maximum Cable Length 50 feet
• Maximum Capacitance/foot 50 pF
• Vmax 25V
• Negative Logic logic 1 -12V, logic-0 12V
  (typical)
• 2 Standard Connectors and Pinouts
• DB9 is the 9-pin connector (DB stands for Data
  Bus)
• DB25 is the 25-pin connector
• NOTE DB25 is a general connector, NOT an RS-232
  Only PC parallel ports commonly use the DB25
  Also!

21
DB25 and DB9 Connectors
22
Basic 232 Specifications
23
TTL Interfacing

• Need Line Driver circuits
• Convert from TTL logic level voltages to RS-232
  levels

24
Basic Control Signals (from DTE point of view!)
Rx - Data Receive (DTE) Tx - Data Transmit
(DTE) RTS - Request to Send Data .(DTE
wants to Transmit) CTS - Clear to Send
.(DCE indicates OK to Receive) DTR -
Data Terminal Ready ...(DTE device present and
ready) DSR - Data Set Ready . (DCE
device present and ready) DCD - Data Carrier
Detect RI - Ring Indicator GND - Common for
All Above Signals
Tx
Rx
RTS
CTS
Phone Line
MODEM
UART
PC
DTR
DSR
DCD
DSR
25
All 25 232 Signals
26
Standard Connector Pinouts
27
Interfacing Non-Modem Peripherals

• Can interface two DTEs
• Must Cross Tx and Dx signals (a Null Modem)

2
2
DTE1
DTE2
3
3
7
7

• Synchronization accomplished by the
• asynchronous frame bits
• i.e. the start and stop bits

28
Handshaking (2 Main Types)

• HARDWARE HANDSHAKING
• uses DTR signal as a BUSY/READY indicator

• SOFTWARE HANDSHAKING
• Uses ASCII characters in data transmission
• Typically a Request Transmission Halt is a
• XOFF (ASCII control Char 13h)
• OR CTRL-S
• Typically a Request Transmission Resume is a
• XON (ASCII control Char 11h)
• OR CTRL-Q

29
16550D UART

• UART Universal Asynchronous Receiver/Transmitter
  
• support chip for serial I/O in x86 architectures
• Original device was 16550, the 16550D contains
  two 16550s (D stands for Dual)
• Function is send and receive data via the
  asynchronous serial protocol

30
Register Set (Data)

• 8 registers total
• On PC, one set mapped to ports 3F8-3FF (COM1),
  other set mapped to 2F8-2FF (COM2)
• Data registers (all 8 bits) (See Table 10.6)
• Receive buffer register (RBR) holds incoming
  serial data (offset 0, read only)
• Transmit holding register (THR) holds outgoing
  serial data (offset 0, write only, name THR)
• Scratch register (offset 7) used to hold
  temporary data
• Receive/Transmit Data registers have FIFOs in
  front of them for more efficient operation.

31
FIFO First In First Out Buffer
BUF
BUF
THR
BUF
Serial ShiftOut
Serial out
8
8
8
8
8
16 byte FIFO
Advantage of a FIFO on output of THR is that
dont have to wait for serial shift out to finish
before we send more data to THR. The THR
contents immediately sent to FIFO. Only have to
wait if FIFO becomes full. If FIFO is not
enabled, then after writing byte to THR, have to
wait until it is shifted out the serial line.
32
FIFO on RBR (Receive Buffer Register)
BUF
BUF
RBR
BUF
Serial ShiftIN
Serial In
8
8
8
8
16 byte FIFO
When 8 bits of serial data arrived, immediately
sent to RBR via FIFO. While waiting for
processor to empty the RBR by reading it,
additional serial data can arrive and is stored
in the FIFO. Processor HAS to read the RBR
before the FIFO becomes entirely full or data
will be lost.
33
Control Registers

• Interrupt Enable Register (IER, offset 1) used
  to enable to interrupts on various conditions
• Data available interrupt
• Transmitter Data Register empty
• FIFO Control Register (FCR, offset 2, write only)
• Used to configure FIFO operation
• Line Control Register (LCF, offset 3)
• sets data format for serial transfer
• Modem Control Register (MCR, offset 4)
• controls modem output handshaking lines

34
Status Registers

• Interrupt Identification Register (IIR, offset 2,
  read only)
• Used to identify source of an interrupt
• Line Status Register (LSR, offset 5)
• status bits to determine when data is received,
  data has been sent, various error conditions
• Modem Status Register (MSR)
• Use to control output handshaking signals for
  modem interface.

35
Port Mapping
36
Send A Byte (Polled I/O)
Transmitter Holding Register Empty?
Check bit 5 in Line Status Register
Write Byte to Transmitter Holding Register
37
Receive A Byte (Polled I/O)
Input Data Ready?
Check bit 0 in Line Status Register
Read Byte from Receive Buffer Register
38
Error Conditions

• Overrun Error (Bit 1 in Line Status Register)
• Did not read Receive Data Register fast enough.
  Incoming data overwrote current data
• Parity Error (Bit 2 in Line Status Register)
• Incoming data had incorrect parity
• Framing Error (Bit 3 in Line Status Register)
• Invalid stop bit received (received too soon or
  too late)

39
Interrupt Conditions

• Use the IER (Interrupt Enable Register) to
  enable interrupt conditions
• Bit 0 enables Received Data Interrupt (generate
  interrupt when data is received)
• Bit 1 enables Transmitter Holding Register Empty
  Interrupt (interrupt when data is finished being
  sent)
• Use the IIR (Interrupt Identification Register)
  to determine what caused an interrupt
• Bit 0 is for received data interrupt
• Bit1 is for THRE interrupt

40
Interrupts and the FIFOs

• Receive Buffer FIFO
• Can program the receive buffer FIFO to generate
  an interrupt when FIFO has either 1, 4, 8 or 14
  bytes in it.
• Bits 7,6 of the FIFO Control register control
  this setting
• Transmit Buffer FIFO
• if Transmit interrupts are enabled and FIFO is
  enabled, then will only generate an interrupt
  when the transmit buffer FIFO is empty.

41
Setting Data Format, Baud Rate

• Line Control Register used to set data format
• number of data bits (5,6,7, or 8)
• number of stop bits (1 or 2)
• Parity on (even or odd), or Off
• To set baud rate, need to set Bit 7 of LCR to a
  1
• This bit is called the Divisor Latch Access Bit
  and changes registers 0,1 to be the low, high
  divider configuration registers
• Programming registers low,high divider register
  will set a divide-by rate of the input clock
  setting a clock speed (table 10.8).
• After setting speed, Bit 7 of LCR needs to be set
  back to 0 for normal operation.