Serial Communication Interface

1
Serial Communication Interface

• Abel Valdes
• Tsun-Yen Wu
• Faisal Tanvir

2
Presentation Outline

• Types of data transmission
• Parallel Communication
• Serial Communication
• Applications
• Serial Communication Transition Formats
• HC11 SCI Registers
• Wakeup, Send Break
• Examples

3
Data Transmission

• Importance
• Most electronic devices must communicate with
  other devices to either control them or send data
  to them
• Standardization
• The two communicating devices must speak the
  same language
• Key Features
• Compatibility
• Data Integrity
• Speed

Abel Valdes
4
Parallel Communication

• Simultaneous 8-bit transmission
• Bits must stay synchronized
• Restricted distance to avoid synchronization
  problems
• Theoretically faster (limited by skew)
• Hardware easier to implement

Abel Valdes
5
Serial Communication

• Transfers one bit at a time
• Requires only one data line
• Slow compared to parallel transmission
• Less expensive

Abel Valdes
6
Serial vs. Parallel

• Clock differences between channels
• No crosstalk between transmission lines

• Serial communication requires less transfer lines

Abel Valdes
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Applications
ATA interface for storage devises (IDE), cable
lengths of up to 18 133 Mbits/sec with 16 bit
lines. Serial ATA 1.5Gbits/sec FireWire 8000
Mbits/sec USB 480 Mbits/sec
Abel Valdes
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Synchronization

• Synchronous
• Data rates determined by clock rates
• Continuous transmission to maintain clock
  synchronization.
• Faster

• Asynchronous
• Transmission can occur at any time
• Receiver is always listening
• No idle characters
• Data words not locked into system timing
• Requires start and stop bits

Abel Valdes
9
Start and Stop Bits

• Start bit
• First bit to be transmitted for each word of data
• A transition from idle state to the opposite
  state, last one bit time
• Stop bit
• Last bit(s) indicates the end of a word
• Value of idle state

0110 0001 6116
Abel Valdes
10
Parity Bit

• Used to check that all of the set bits were
  received
• Odd parity bit is set to 1 or 0 to make the sum
  of all bits odd.
• Even parity makes the sum of all bits even.
• Not implemented in HC11

Sum 4
Transmitted
Start 0 1 1 1 0
1 0 0 Parity Stop
Received
Sum 3
Start 0 1 1 0 0
1 0 0 Parity Stop
Parity bit sent (1) Parity of signal received
(0)
Abel Valdes
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Transfer Rates

• Baud Rate number of individual states that are
  transmitted per second.

Data Rate (bps) Max Distance (ft)
19200 45
9600 76
4800 152
2400 304
1200 608
600 1216
8 bits of information Start bit Stop
bit_______________ 10 bit word
Abel Valdes
12
Transmission Rates Example

• Example
• Consider baud rate 4800 baud
• 12 bits/word 1 start bit 8 data bits 1
  parity bit 2 stop bits
• Bit time 1/(baud rate) 1/4800baud
  0.208ms/bit
• Word time (12 bits)(bit time) 2.5ms
• Word rate 1/(word time) 400 words/s
• Bit rate (word rate)(8 data bits) 3200
  bits/s

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Signal Standard

• Serial devices convert TTL/CMOS-level signals to
  higher voltage bipolar signals
• state 1 -3V to -25V
• state 0 3V to 25V

Bit Period Transition Time
lt125 µs 5 µs
25 ms 125 µs 4 of bit period
gt25 ms lt 1ms
Abel Valdes
14
Asynchronous Serial Transmission
One Data Packet

• Four parts per packet

Parity Bit
Data Bit 1
Data Bit 3
Data Bit 6
HIGH
Stop Bit
LOW
Data Bit 0
Data Bit 2
Start Bit
Data Bit 4
Data Bit 5
Data Bit 7
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Start bitIdeal Case
(0) sampling clock (RT clock) 16 times the
baud-rate frequency(1) idle-line time(2)
logic-zero sample is preceded by three logic-one
samples start-bit qualifiers(3)
start-verification samples(4) data samples
Tsun-Yen Wu
16
Noise (i)
Noise
Data receiving aborted!!!
Tsun-Yen Wu
17
Noise (ii)
Tsun-Yen Wu
18
HC11 SCI Registers

• 5 Main Registers
• BAUD Sets bit rate for SCI
• SCCR1 Sets control bits for the 9-bit character
  format and the receiver wake up feature
• SCCR2 Main control register
• SCSR Status Register
• SCDR Main Data Register

Tsun-Yen Wu
19
HC11 SCI Registers
BAUD Register

• Used to set bit rate of SCI system
• TCLR Clear baud rate timing chain bit
• SCP1 SCP0 Baud rate pre-scale select bits
• RCKB SCI baud rate clock test bit
• SCR2 SCR0 SCI baud rate select bits

Tsun-Yen Wu
20
BAUD Register
Tsun-Yen Wu
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BAUD Register
Tsun-Yen Wu
22
HC11 SCI Registers
SCCR1 Register

• Contains control bits related to the 9-bit data
  character format and receiver wake up feature
• R8 Receive data bit 8
• T8 Transmit data bit 8
• M SCI character length bit
• WAKE Wakeup method select bit
• Bits 0, 1, 2 5 Not used (always 0)

Tsun-Yen Wu
23
HC11 SCI Registers
SCCR2 Register

• Main control register for SCI sub-system
• TIE Transmit interrupt enable bit
• TCIE Transmit complete interrupt enable bit
• RIE Receive interrupt enable bit
• ILIE Idle-line interrupt enable bit
• TE Transmit enable bit
• RE Receive enable bit
• RWU Receiver wakeup bit
• SBK Send break bit

Tsun-Yen Wu
24
HC11 SCI Registers
SCSR Register

• SCI status register
• TDRE Transmit data register empty bit
• TC Transmit complete bit
• RDRF Receive data register full bit
• IDLE Idle-line detect bit
• OR Overrun error bit
• NF Noise flag
• FE Framing Error bit
• Bit 0 is not used (always 0)

Tsun-Yen Wu
25
HC11 SCI Registers
SCDR Register

• SCI data register
• Two separate registers
• When SCDR is read, the read-only RDR is accessed
• When SCDR is written, the write-only TDR is
  accessed
• R7 - R0 Read bits
• T7 - T0 Write bits

Tsun-Yen Wu
26
Wake Up

• M68HC11 supports a receiver wake up function,
  which is intended for systems having more than
  one receiver
• The transmitting device directs messages to an
  individual receiver or group of receivers by
  passing addressing information in the initial
  byte
• Receivers not addressed activate the receiver
  wakeup function
• -This makes these receivers dormant for the
  remainder of the unwanted message
• Software in the receiver evaluates if the data is
  intended to a receiver.

Faisal Tanvir
27
Wake Up Cont.

• Two methods of Wakeup
• Idle Line wake up as soon as RxD line becomes
  idle. All devices are awake (RWU0) until they
  realize that the message is not intended for
  RWU1. Then wake up when a idle line of 10 RxD
  is detected.
• Note 1 bit time between idle and message and no
  space in message.
• Address-Mark the most significant bit use to
  indicate if is data(0) or address(1) all dormant
  receivers wake up if one is detected. Check if
  message is for them.
• Note no idle between messages and space in
  message ok.

Faisal Tanvir
28
Send Breaks

• Break characters are character length periods
  when the TxD line goes to 0.
• Either 10 or 11 0s.
• As long as the SBK bit is set, break characters
  will be sent.
• Character length is influenced by the M bit in
  the SCCR1
• M 0 All characters are 10 bit times long
• M 1 all characters are 11 bit times long
• Break characters have no start and stop bits

Faisal Tanvir
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SCI Transmitting and Receiving with the HC11
Faisal Tanvir
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Transmitting and Receiving with HC11

• Receiver uses pin 0 of port D
• When SCI receiver is enabled DDRD0 is set to
  zero to disable output buffer.
• Transmitter uses pin 1 of port D
• When SCI transmitter is enabled DDRD1 is set
  to one to disable input buffer.
• The original state of DDRD is restored once
  transmitting/receiving has ended.

Faisal Tanvir
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Transmitter Block Diagram
Faisal Tanvir
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Transmitting Steps

• 1. Set Baud rate to equal receiver
• 2. Set TE (SCCR2) high to enable
• 3. Set Wake Up mode (SCCR1)
• 4. TE sends idle character to wake receiver
• 5. Receiver determines if message is intended for
  it
• 6. Load character into SCI Data Register (SCDR)
• 7. Character placed in shift register and shifted
  out
• 8. When TDRE (SCSR) sets back to 1, load another
• character (both polling and interrupts can be
  used).
• 9. Transmission complete (TC in SCSR)
• 10. Idle line rests at logic 1, RWU goes to 0

Faisal Tanvir
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Receiver Block Diagram
Faisal Tanvir
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Receiving Steps

• 1. Set Baud rate in Baud register (102B)
• 2. Set bit 4 in SCCR1 (102C) to select 8 or 9
  bit characters set bit 3 to select wake up mode
• 3. Set bit 2 in SCCR2 (102D) to enable receiver
  set bit 4 to enable interrupt on idle set bit 5
  to enable interrupt when character received or
  overrun occurs.
• 4. Read status of receive from SCSR (102E) Bit 5
  will be set when data is received framing error
  sets bit 1 noise sets bit 2 overrun sets bit 3
  idle sets bit 4
• 5. Read data received from SCDR (102F)
• 6. If 9 bit data format is used, the ninth bit of
  data will be located in bit 7 of SCCR1 (102C)

Faisal Tanvir
35
Examples of SCI
Transmit - Configuration

• Lets say we want to transmit hex number 2C at a
  Baud rate of 1200
• First set up variables and set Baud rate

MAIN EQU 1040 SCCR2 EQU 102D BAUD EQU
102B SCSR EQU 102E SCDR EQU 102D
Assemble code starting here Address of SCI
control register 2 Address of Baud rate control
register Address of SCI status register Address
of SCI data register
Faisal Tanvir
36
Examples of SCI
Transmit
ORG MAIN LDAA 33 STAA BAUD LDAA
08 STAA SCCR2 LDAA 2C STAA
SCDR CHECK LDAA SCSR ANDA C0 CMPA
C0 BNE CHECK SWI
This sets bits like in last slide Write to the
Baud register Set the Transmit Enable bit
high Write to SCCR2 Put you data to transmit
here Store it in the SCI data register Load the
status register to Acc A Check to see if Transmit
Complete flag is set If it is not, loop and keep
checking If it is, were done
Faisal Tanvir
37
Examples of SCI
Receive- Configuration

• Once again, Baud rate of 1200
• Set up things in a similar way

MAIN EQU 1041 SCCR2 EQU 102D BAUD EQU
102B SCSR EQU 102E SCDR EQU 102F STORE EQU
1040
Assemble code starting here Address of SCI
control register 2 Address of Baud rate control
register Address of SCI status register Address
of SCI data register Address of place to store
incoming data
Faisal Tanvir
38
Examples of SCI
Receive
ORG MAIN LDAA 33 STAA BAUD LDAA
04 STAA SCCR2 CHECK LDAA
SCSR ANDA 20 CMPA 20 BNE
CHECK LDAA SCDR STAA STORE SWI
This sets bits like in previous slide Write to
the Baud register Set the Receive Enable bit
high Write to SCCR2 Load the status register
into Acc A Check to see if RDRF flag is
set (Receive Data Register Full) If not, keep
checking until it is When data has been received,
store it
Faisal Tanvir
39
References

• General Information
• http//www.ee.nmt.edu/rison/ee308_spr99/lectures.
  html
• http//www.ece.northwestern.edu/local-apps/matlabh
  elp/techdoc/matlab_external/ch_seri8.html
• RS-232 Standard
• http//www.camiresearch.com/Data_Com_Basics/RS232_
  standard.htmlanchor1181440
• http//www.acumeninstruments.com/Support/documenta
  tion/SerialPortBasics/index_pg6.shtml
• M68HC11 Reference Manual
• Previous Student Lectures

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Questions
?
Faisal Tanvir Abel Valdes Tsun-Yen Wu
41
Asynchronous Serial Transmission
Parity Bit

• Used to check for errors
• Helps verify signal integrity
• 2 Types
• -Even makes sum of all high bits
• INCLUDING parity bit EVEN
• -Odd makes sum of all high bits
• INCLUDING parity bit ODD
• Not applicable to HC11

Parity Bit (H or L)
Data Bit 7
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An example of even parity
parity
start
stop
0x52
?
Start Bit
Data Bit 0
Data Bit 1
Parity Bit
Stop Bit
Stop Bit
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
0
1
1
1
0
0
1
0
1
0
0
1
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Asynchronous Serial Transmission
Stop Bit

• Stop bit indicates all data has been transmitted
• 1 or 2 Stop bits

Stop Bit 1
Stop Bit 2
Parity or Bit 7
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Asynchronous Serial Transmission

• Transmitter and receiver operate independently-
  Same baud rate- Same data format
• Requires a start and stop bit to identify each
  byte of data

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Asynchronous Transmission Format

• Bit Types
• Start Bit
• Data Bits
• Parity Bit
• Stop Bit
• Bit types are used to differentiate between words
• For HC11, 10 or 11 bits

46
Asynchronous Serial Transmission
Start Bit

• If line is idle, it continuously sends high (1)
  logic bit
• Each word preceded by start bit
• Signals receiver that data is about to be
  transmitted
• Low (0) logic bit

Previously HIGH
Start Bit
Now LOW
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Asynchronous Serial Transmission
Data Bits

• The content of the package
• Usually 8 bits
• LSB sent First

Ex This transmitted word is 10111001, or B9
LSB
MSB
Data Bit 0
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 7
Data Bit 2
Data Bit 1
Data Bit 6
FLOW