68HC11 Serial IO

1
68HC11 Serial I/O

• Chapter 11

2
Parallel I/O
Multiple I/O lines to transfer data from 6811 to
Ext Device
3
Serial I/O
Minimum of two lines needed to transfer data
from 6811 to Ext Device
4
Why Serial I/O?

• Simple to implement.
• Can be very slow. Sending one bit at a time
• We must send synchronization and/or error
  checking bits with every data packet.
• This adds overhead to our data transmission.

5
Parallel Data Transfer Example

• Assume an 8-bit parallel interface with a
  transfer rate of 1Megabyte/s.
• How long will it take to transfer a 15Megabyte
  file?

6
Parallel Data Transfer Solution

• Assume an 8-bit parallel I/O interface with a
  transfer rate of 1Megabyte per second.
• How long will it take to transfer a 15Megabyte
  file?

Transfer time 15 Megabytes 1 second/Megabyte
15 seconds
7
Serial Data Transfer Example

• Assume an serial interface with a transfer rate
  of 1Megabit per second. Also, assume an overhead
  of 2 bits for each byte of data transferred.
  That is, we need to send 10 bits for every 8 bits
  of data transferred.
• How long will it now take to transfer a
  15Megabyte file?

8
Serial Data Transfer Solution

• Transfer rate 1Megabit/s
• Overhead is 2 bits/byte
• How long will it now take to transfer a
  15Megabyte file?
• Solution
• Total Megabits 15 Megabytes(10 bits/byte)
• 150 Megabits
• Transfer time
• 150 Megabits (1 second/Megabit) 150
  seconds
• Note this is 10x the parallel transfer
  rate

9
68HC11 Serial I/O

• Two types
• SCI Serial Communications Interface
• Asynchronous No clock needed
• SPI Serial Peripheral Interface
• Synchronous Clock needed

10
Asynchronous Serial I/O
Minimum of two lines needed to transfer data
from 6811 to Ext Device
11
Synchronous Serial I/O
Three lines needed to transfer data from 6811 to
Ext Device Extra line is used for clock line.
12
Using the Asynchronous Serial I/O(Ser. Comm.
Iface.) on the 68HC11

• Initialize the interface
• Data rate (baud rate)
• Word length
• Interrupts, if needed
• Write to the Data Register
• Read from the Data Register

13
Initializing the Interface

• Polling Method

14
Top Level Pseudo-Code68HC11

• Initialize the interface
• Set baud rate
• Set Mode
• Turn-on transmitter and receiver

15
Initializing the Interface

• Set the Baud Rate

16
Baud-102B Baud Rate Control Reg

SCR0
SCR1
SCP0
RCKB
SCP1
0
TCLR
SCR2
Bits
Scp1 Scp0 Scr2 Scr1 Scr0 Baud Rate 0 0
0 0 0 125K 1 1 0
0 0 9600 1 1 0 0
1 4800
Other bits used for test mode
17
Initializing the Interface

• Set the Mode

18
SCCR1 - 102CSCI Control Register 1
0
0
M
0
T8
R8
Wake
0
Bits
T8 Transmit Bit 8 used for 9-bit data

R8 Receive Bit 8 used for 9-bit data
M Mode Select 0 1 start bit, 8 data
bits, 1 stop bit 1 1 start bit, 9 data
bits, 1 stop bit
19
Initializing the Interface

• Turn on the transmitter and receiver

20
SCCR2 - 102DSCI Control Register 2
SBK
RWU
ILIE
RIE
TCIE
TIE
TE
RE
Bits
TE Transmit Enable 0 Disable
(default) 1 Enable This bit should
be 1 to use Port D for serial I/O
RE Receiver Enable 0 Disable
(default) 1 Enable This bit should
be 1 to use Port D for serial I/O
21
Initializing the Interface

• Pseudo-code
• 68HC11 Code

22
Pseudo-code Initialize the Serial Port

• SCCR1 ? Mode_Configuration_byte
• CB 00000000 1 start, 8 data, 1 stop
• Baud ? Baud_Configuration_byte
• CB 00110000 9600 baud
• SCCR2 ? TR_Configuration_byte
• CB 00001100 Xmit and Rcvr Enable

23
68HC11 Assembly languageInitializing the Serial
Port

• Assume Baud1028, SCCR1102C, and
  SCCR2102D
• LDAA MODE_CB
• STAA SCSR1
• LDAA Baud_CB
• STAA BAUD
• LDAA TR_CB
• STAA SCSR2

24
SCI Initialization Example (AS11)

• ONSCI LDAA SCP1SCP0 9615 baud
• STAA BAUD set it
• CLR SCCR1 8 bits
• LDAA TERE enable T/R
• STAA SCCR2 make it so
• RTS
• This works, given appropriately defined
  labelsBAUD, SCCR1, SCCR2 for the SCI registers
• and bit-mask symbols SCP1,SCP0,TE, RE.

25
SCI Initialization Example (C)

• void onsci()
• BAUD SCP1SCP0 /9600 baud/
• SCCR1 0 /8 bits/
• SCCR2 TERE /enable/
• This assumes BAUD, SCCR1, SCCR2 are previously
  defined char constants.
• SCP1,SCP0,TE,RE are char constants for the
  appropriate bit masks.

26
Writing to the data register

• Polling

27
Top Level Pseudo-Code68HC11

• Writing to the serial output port (polling)
• Repeat
• Until Transmit_bufferempty
• SCDR ? A assume A register holds data

28
Writing to the data register

• Checking Transmit Buffer

29
SCSR-102E SCI Status Reg

• Check status bit TRDE1 before writing new data

0
FE
IDLE
OR
RDRF
TC
TDRE
NF
Bits
TRDE Transmit data register empty flag
0 not empty. Data are still loaded in SCDR
from transmission 1 empty. SCDR
is empty. The next byte can be written to SCDR
TC Transmit complete flag 0
Transmitter is busy sending a character
1 Transmitter is done sending the last
character. This bit checks the output
shift register which is used by TXD
30
Writing to the data register

• Transmitting the Data

31
SCDR - 102F SCI Data Register

• To transmit data, write to register SCDR 102F

T1
T4
T2
T3
T5
T6
T7
T0
Bits
XNot Used BBidirectional
32
Pseudo-code Writing to the Serial Port

• Assume data are in the A register
• Repeat
• Until TRDE1
• SCDR ? A
• Return

33
Assembly ExampleWriting to the Serial Port

• OUTPUT BRCLR SCSR,X TDRE OUTPUT
• ANDA 01111111 clr b7
• STAA SCDR,X send it
• RTS
• Assumes SCSR2E, SCDR2F, X1000 (base of
  registers), TDRE80.

34
C language version

• void output(const char a)
• while (!(SCSRTDRE))
• /do nothing but wait/
• SCDR aBIT7
• This assumes that SCSR, SCDR are appropriate char
  pointers.
• And that TDRE BIT7 0x80.

35
Block DiagramWriting to Serial Port
102F
STAA SDSR
TDRE1 when all bits have been transferred to
Parallel to Serial Buffer
8-bits
Parallel to Serial Buffer
1 bit
PD1
Serial Out
36
Port D - 1008 Serial I/O Register

• Serial output bit PD1

TXD
SCK
MISO
MOSI
SS
1
0
RXD
Bits
XNot Used BBidirectional
37
Reading from the data register

• Polling

38
Top Level Pseudo-Code68HC11

• Reading from the serial output port (polling)
• Repeat
• Until Receiver_bufferfull
• A ? SCDR

39
Reading from the data register

• Checking Receiver Buffer

40
SCSR-102E SCI Status Reg

• Check status bit RDRF to determine when to read
  the next byte.

0
FE
IDLE
NF
OR
RDRF
TC
TDRE
Bits
RDRF Receiver data register flag full
0 Data register is not full.
1 Data register has new data
Idle Idle line detected flag 0
The receive line is active (or has not been
active since last IDLE) 1 The
receive line has become idle Used in
half-duplex mode
41
SCDR - 102F SCI Data Register

• To receive data, read location SCDR 102F

R1
R4
R2
R3
R5
R6
R7
R0
Bits
XNot Used BBidirectional
42
Pseudo-code Reading from the Serial Port

• Assume data are stored in the A register
• Repeat
• Until RDRF1
• SCDR ? A
• Return

43
68HC11 Code Reading from the Serial Port

• Assume data are in the A register
• Assume SCSR102E and SCDR102F
• RDRF 00100000
• LDX SCSR
• Wait BRCLR 0,X RDRF Wait
• LDAA SCDR
• RTS

44
Block DiagramReading from Serial Port
102F
LDAA SDSR
RDRF1 when all bits have been loaded from
serial to parallel buffer
8-bits
Serial to Parallel Buffer
Serial In
PD0
1-bit
45
Parity
46
XOR GATE
Equation
Symbol
Truth Table
47
XNOR GATE
Equation
Symbol
Truth Table
Equivalence Function
48
Parity

• Use extra bit for error checking or parity
• Two types with one bit
• Odd Parity Number of ones in dataparity is
  odd.
• Even Parity Number of ones in dataparity is
  even.
• Transmitter generates parity bit
• Use XOR/XNOR function.
• Odd Parity XNOR of all of the data bits
• Even Parity XOR of all of the data bits
• Receiver checks parity bit
• Use same function of all bits (including parity)
• If output is one, a parity error has occurred

49
Parity Example

• Assume even parity and given Serial data 32
• In binary 00110010
• we have 3 bits (odd), so we XOR all of the data
  bits and find that the parity bit is 1, which
  makes the total number of bits even.
• i.e. 1,00110010
• Lets assume no errors in the transmission, at
  the receiver, we also have 1,00110010
• Check parity XOR of 100110010 0
• No error in transmission

50
Parity Example

• Assume even parity and given Serial data 32
• In binary 00110010
• we have 3 bits (odd), so we XOR all of the data
  bits and find that the parity bit is 1, which
  makes the total number of 1 bits even.
• i.e. 1,00110010
• Lets assume a single bit error in the
  transmission, at the receiver, we have
  1,00110011
• Check parity XOR of 100110011 1
• ERROR in transmission
• Note
• with only one bit, we can only DETECT a single
  bit error.
• If two bits are in error, our system will NOT
  detect the error
• Using more bits allows us to Detect and Correct
  error.
• Hamming Codes Digital Communications

Error
51
Parity in 68HC11
52
SCCR1 - 102CT8,R8, and M bits
0
0
M
0
T8
R8
Wake
0
Bits
Must generate and check parity manually!!!
T8 Transmit Bit 8 used for parity data

R8 Receive Bit 8 used for parity data

M Mode Select (use mode1 for parity) 0
1 start bit, 8 data bits, 1 stop bit 1
1 start bit, 9 data bits, 1 stop bit
53
TPS Quiz
54
Simulation Example
55
Other SCSR bits
56
SCSR-102E SCI Status Reg

• Other status bits

0
FE
IDLE
OR
RDRF
TC
TDRE
NF
Bits
OR Receiver overrun error full
0 No overrun error 1 An
overrun has occurred. Overrun occurs
if new character has been received before old
data have been read. The new data are
lost.
NF Noise Flag 0 No noise
detected during last character read.
1 Noise detected. 6811 samples each
data bit three times, different answers will set
NF
57
SCSR-102E SCI Status Reg

• Other status bits

0
FE
IDLE
OR
RDRF
TC
TDRE
NF
Bits
FE Framing Error 0 No
framing error 1 Framing error
has occurred. If the stop bit is not
detected correctly, a framing error will occur.
58
Interrupts
59
Top Level Pseudo-Code68HC11

• Configure Interrupt Vector Table (IVT)
• Initialize the interface
• Set baud rate
• Set Mode
• Turn-on transmitter and receiver
• Turn-on interrupts
• TIE bit (Bit 7) in SCCR2 for Transmitter
• RIE bit (Bit 5) in SCCR2 for Receiver
• Normally, only turn one of them on at a time!!!
• Enable maskable interrupts (CLI)

60
ISR Pseudo-Code68HC11

• Temporarily disable additional interrupts
• We dont want our ISR interrupted
• Acknowledge the interrupt request
• Device sending the request will quit asking for
  service
• Service the Interrupt
• Return from the Interrupt

61
Interrupt Control Bits

• TIE and RIE

62
SCCR2 - 102DTIE
SBK
RWU
ILIE
RIE
TCIE
TIE
TE
RE
Bits
TIE Transmit Interrupt Enable 0
Disable (default) 1 Enable When
enabled, generates an SCI interrupt when SCDR is
empty
TCIE Transmit Complete Interrupt Enable
0 Disable (default) 1 Enable
When enabled, generates an SCI interrupt with
the output register is empty.
63
SCCR2 - 102DRIE
SBK
RWU
ILIE
RIE
TCIE
TIE
TE
RE
Bits
RIE Receive Interrupt Enable 0
Disable (default) 1 Enable This bit
should be 1 to used Port D for serial I/O
ILIE Idle line Interrupt Enable 0
Disable (default) 1 Enable When
enabled, generates an interrupt when the serial
line is idle.
64
Pseudo-code Initialize the Serial Port

• SCCR1 ? Mode_Configuration_byte
• CB 00000000 1 start, 8 data, 1 stop
• Baud ? Baud_Configuration_byte
• CB 00110000 9600 baud
• SCCR2 ? TR_Configuration_byte
• CB 00001100
• Setting the interrupts,
• SCCR2 ? Interrupt_Configuration_byte
• CB CB 10000000 (Transmitter)
• CB CB 10000000 (Receiver)

65
68HC11 Assembly languageInitializing the Serial
Port

• Assume Baud1028, SCCR1102C, and
  SCCR2102D
• LDAA MODE_CB
• STAA SCCR1
• LDAA Baud_CB
• STAA BAUD
• LDAA TR_CB INT_CB
• Enable transmitter and receiver, turn on
  interrupt
• STAA SCCR2
• CLI Clears Interrupt mask to enable
  interrupts

66
68HC11Writing Serial Port

• Writing to the serial output port (interrupts)
• Assumes only xmit interrupts enabled
• The ISR assumes SCDR102F
• isr
• SEI Temporarily disable
  additional interrupts
• LDAA SCSR Turn off the transmitter interrupt
  request
• STAA SCDR Write serial data
• RTI Return from Interrupt. This will
  enable interrupts again
• ---------------------
• SCI_IVT EQU FFD6
• ORG SCI_IVT This sets the SCI
  IVT to ISR
• FDB ISR

67
68HC11Reading Serial Port

• Reading from the serial output port (interrupts)
• Assumes only receive interrupts enabled
• This is the ISR. Assume SCDR102F
• isr
• SEI Temporarily disable
  additional interrupts
• LDAA SCSR This turns off the receiver
  interrupt request
• LDAA SCDR Read serial data
• RTI Return from Interrupt. This will enable
  interrupts again
• ----------------------------------------
• SCI_IVT EQU FFD6
• ORG SCI_IVT This sets the
  SCI_IVT to ISR
• FDB ISR

68
Note

• If both receiver and transmitter interrupts are
  enabled, your ISR must determine which one
  generated the interrupt. This is accomplished by
  examining the TDRE, RDRF, and OR bits in the SCSR
  (102E) register.

69
End of slides
70
Port D - 1008 Serial I/O Register

• Writing data

TXD
SCK
MISO
MOSI
SS
1
0
RXD
Bits
XNot Used BBidirectional
71
SCDR - 102F SCI Data Register

• Reading data

R1
R4
R2
R3
R5
R6
R7
R0
Bits
XNot Used BBidirectional
72
SCSR-102E SCI Status Reg

0
FE
IDLE
OR
RDRF
TC
TDRE
NF
Bits
73
SPCR - 1028 SPI Control Register
SPR0
SPR1
MSTR
DWOM
SPE
SPIE
CPOL
CPOH
Bits
SPIE SPI System Enable 0 Disable
(default) 1 Enable This bit should
be 0 to used Port D for parallel I/O
DWOM Port D Wire-OR Mode 0 Normal
Outputs (default) 1 Open Drain
Outputs
74
SCCR2 - 102DSCI Control Register 2
SBK
RWU
ILIE
RIE
TCIE
TIE
TE
RE
Bits
TIE Transmit Interrupt Enable 0
Disable (default) 1 Enable When
enabled, generates an SCI interrupt when SCDR is
empty
TCIE Transmit Complete Interrupt Enable
0 Disable (default) 1 Enable
When enabled, generates an SCI interrupt with
the output register is empty.
75
SCCR2 - 102DSCI Control Register 2
SBK
RWU
ILIE
RIE
TCIE
TIE
TE
RE
Bits
RIE Receive Interrupt Enable 0
Disable (default) 1 Enable This bit
should be 1 to used Port D for serial I/O
ILIE Idle line Interrupt Enable 0
Disable (default) 1 Enable When
enabled, generates an interrupt when the serial
line is idle.
76
SPCR - 1028 SPI Control Register
SPR0
SPR1
MSTR
DWOM
SPE
SPIE
CPOL
CPOH
Bits
SPIE SPI System Enable 0 Disable
(default) 1 Enable This bit should
be 0 to used Port D for parallel I/O
DWOM Port D Wire-OR Mode 0 Normal
Outputs (default) 1 Open Drain
Outputs
77
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