Memory Management

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Memory Management
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Memory Management
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Memory Hierarchy
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Memory Manager
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Background
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Binding of instructions and Data to Memory
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Address Binding CNTD

• Source program references data and instructions
  using identifiers (e.g. variable names etc.)
• Compiler translates source program into object
  module.
• A collection of object modules is combined using
  a link editor to produce an absolute module.
• Can compiler/linker generate physical addresses?
• Actual physical addresses are not known yet. Why
  Not?
• Link editor produce re-locatable code all
  addresses are relative to memory address 0
• gt compile-time binding

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Address Binding CNTD

• When module is loaded in memory for execution the
  loader, knowing where module is to be loaded in
  memory, can set the addresses at load time to
  produce the executable image of the module with
  physical addresses
• gt load time binding
• What if module is swapped out of memory?
• Dynamic Binding binding is delayed until
  execution time. At load time, each identifier is
  associated a relative address. Physical address
  is computed at execution time by hardware .

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Dynamic Address Binding

• All addresses to data and instructions are made
  relative to beginning of the module i.e. as if
  process address space starts at physical address
  0.
• Hardware provides a base register (also called a
  relocation register).
• When process is switched to CPU the base register
  is loaded with the initial address of the module.
• At run time

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Dynamic Address Binding
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Logical Address vs. Physical Address

• The concept of logical address space that is
  bound to a physical address space is central to
  contemporary memory management.
• Logical address address generated by user
  program (also referred to as virtual address).
• Physical address address seen by the memory unit.

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Memory Management Unit (MMU)

• The hardware unit that maps logical addresses to
  physical addresses.
• For the dynamic address binding scheme, the MMU
  intercepts each logical address generated by the
  program and translates it into its equivalent
  physical address. It can also provide some basic
  memory protection

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Dynamic Binding with Memory Protection
Logical Address
Base Register
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Memory Allocation

• Given a set of processes waiting to be loaded in
  memory, how is memory space allocated to
  processes
• Contiguous Allocation
• Paging
• Segmentation

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Contiguous Allocation

• Main Memory is divided in two main partitions
• Resident operating system (usually held in low
  memory with interrupt vector)
• User processes held in high memory

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Contiguous Allocation

• Processes are allocated memory in contiguous
  blocks
• gt end up with multiple
• blocks some allocated and
• some free.
• Fixed size partitions
• Variable size partitions

OS
Process 1
Process 3
Process 5
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Fixed Size Partitions
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Fixed Size Partitions
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Variable Size Partitions

• OS maintains list of allocated blocks and list of
  free blocks (holes).
• OS maintains one queue of processes on free list
• When a process arrives, it is allocated memory
  from a hole large enough to accommodate it.

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Variable Size Partitions
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Variable Size Partitions
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Dynamic Storage-Allocation Problem
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Paging
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Paging Cont.
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Page Table
Main Memory
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Address Translation Scheme
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Address Translation Architecture
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Example

• Main memory size 64 K bytes
• frame/page size 512 bytes
• Number of bits in the physical address?
• Memory size 64 K 64 1024 216
• address width log2 (memory size) 16 bits
• Number of bits in offset field of address?
• Offset field indicates distance inside a page
• bits in offset field log2 (page size) 9
  bits
• Number of bits in the frame field of address?
• bits in frame field log2(Number of frames in
  main memory)
• Number of frames memory size/frame size 128
• bits in frame field log2(memory size/frame
  size)
• 7 bits.
• Note frame field offset field address width

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Another Example

• Main Memory Size 32 K
• page size 4 K
• address field?
• Etc.
• Process P logical address space 0 - 12,888
• gt 4 pages page 0 - page 3
• Assume P's page table is as follows
• What is the physical address of logical address 0
  of process P?
• What is the physical address of logical address
  10000?

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Example--Paging
Process A
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Memory Protection
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Memory Protection--Example

• Memory address size 16 bits
• address range 0 thru 65, 535
• Frame size is 2K
• 32 frames frame 0 - frame 31
• Process P1 has address range 0 - 12,688
• 12,688/2K 6.19 gt need 7 pages
• gt process P1 address range is page 0 thru page
  6
• Memory Protection two options
• 1. Page table list all frames. Use valid/invalid
  bit in each entry of page table
• 2. Page table contains only frame of pages
  used by process gt Use a Page Table Limit
  Register

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Internal Fragmentation--Example Cont.

• Process P1 address space 0-12,688
• page 0 - page 6
• in last page, only addresses 12,288 - 12,688 are
  legal
• the rest of the page is "empty"
• gt Internal fragmentation
• On average, 1/2 page per process is wasted to
  fragmentation
• gt fragmentation increases with larger page
  size

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Implementation of a Page Table

• Page table is kept in memory.
• Page-table base register (PTBR) points to the
  page table.
• Page-table length register(PTLR) indicates the
  size of the page table.
• Two major problems
• 1. every data/instruction access requires two
  memory accesses. One for the page table and one
  to access data/instruction
• 2. Page table takes up memory space.

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Two-memory Access Problem

• Can be solved by the use of a special
  fast-lookup hardware cache called associative
  register or Table Look-aside Buffer (TLB).
• TLB is contained within the CPU
• TLB is used to cache that part of the page table
  that is "most likely" to be referenced in the
  future.

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Translation Look-aside Buffer
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Effective Access Time--Example

• Memory access time Tmm 100 nsec
• Time to search the TLB 20 nsec
• TLB hit ratio 98
• What is the effective access time?
• Effective Tmm 0.98 (10020) 0.02 (210020)
• 122 nsec
• Memory Access time penalty for paging 22

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Page Table Size

• Assume an address space of 232 bytes
• address size 32 bits
• Frame size 4K
• gt of frames 232/4K 220 frames
• gt page table for a given process may have up to
  1 million entries
• gt each address requires 32 bits 4bytes
• gt 4 mega bytes per page table
• Page size Trade-off size of page table vs
  fragmentation
• Page table may be too large to be stored in a
  contiguous block of memory gt page the page
  table

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Two-Level Paging
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Two-level Paging

• Assume an address space of 232 bytes
• address size 32 bits
• Frame size 4K 212 bytes
• gt of frames 232/4K 220 frames
• gt page table 4 bytes per entry
• gt page table requires up to 222 bytes
• gt page table requires up to 222 / 212 210
  frames

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Two-Level Paging
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Multilevel Paging and Performance

• A memory access operation requires three access
  to physical memory.
• Caching can improve performance
• Assume a TLB with a 98 hit rate
• memory access time 100 nsec
• TLB access time 20 nsec
• Note TLB contents is as for 1-level paging
• Effective memory access time 0.98120
  0.02320
• 124 nsec
• Performance penalty for paging 24

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Inverted Page Table

• One page table for all processes in the system
• Page table has one entry per physical frame of
  memory
• Each entry consists of
• frames number (table index)
• Process ID that owns the frame
• Logical page number
• If a frame is empty, it is marked as invalid.
• Logical address ltPID, page number, offsetgt
• Page table is searched for a match
• Advantage reduce memory required to store page
  table(s)
• Disadvantage need to perform a search when
  mapping logical to physical addresses.

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Inverted Page Table Architecture
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Segmentation
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Logical View of Segmentation
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Segmentation Architecture
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Segmentation Architecture
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Segmentation Architecture
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Segmentation With Paging

• Problem of segmentation
• external fragmentation
• Segments may be so large that it becomes
  difficult to find a contiguous block big enough
  to hold it.
• gt page the segments
• break each segment into a set of equal size
  pages.
• Note logically each segment will consist of N
  pages numbered page 0, page 1, , page (N-1)

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Segmentation With Paging (cont.)

• Each page is assigned to a physical frame in
  memory.
• Need a page table for each segment.
• Address translation
• logical address ltsegment-number, offsetgt
• segment-number points to an entry in segment
  table that points to the base address of the page
  table of that segment.
• The offset is broken into two parts page number
  and offset within the page.
• Page number is use to index into the page table
  and get the physical frame number.

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Address Translation in MULTICS
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