Single Event Effects of a FLASH-based FPGA

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Single Event Effects of a FLASH-based FPGA

• J. J. Wang, Brian Cronquist, John McCollum
• Actel Corporation
• Rich Katz, Igor Kleyner (OSC) - NASA/GSFC
• Rocky Koga - Aerospace

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Outline

• Device and Technology
• Architecture
• Beam Tests and Results
• Conclusions

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ProASIC
ProASIC is a register rich FLASH-based FPGA
family manufactured by 0.25µm technology and
offering up to half million system gates.
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ProASIC Plus
ProASIC Plus is an improved ProASIC manufactured
by 0.22µm technology and above, offering up to 1M
system gates.
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FPGA Switch Technology
SRAM FLASH Antifuse
Re-programmable Re-programmable One time programmable
Volatile Non-volatile Non-volatile
Standard CMOS FLASH Technology Special process
Very sensitive to SE Insensitive to SE Immune to SE
In operation mode, not programming mode

• SEE of FLASH-based FPGA comes only from its CMOS
  logic.

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The FLASH Switch
The switch is comprised of two transistors which
share a gate.
Additional source/drain implant in PRG/SEN device
enables tunneling to overlapping floating
gate. ONO inter-poly dielectric
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Program and Erase
Program and erase are accomplished with F-N
Tunneling where the floating gate overlaps the
source and drain.
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Operation
During operation, the floating gate is
effectively 1.5VCC in the on state and slightly
negative in the off state.
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Comparison with SRAM Switch
The FLASH switch is approximately 1/7th the area
of an SRAM switch.
SRAM based PLD
FLASH based PLD
7 1
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Outline

• Device and Technology
• Architecture

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Chip Layout
ProASIC contains standard elements of any FPGA
Logic Cells, IO, Embedded SRAM and Routing
Resources
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Logic Tile
The ProASIC logic tile is a fine grained FPGA.
Configured with switches. Primitive register
with set/reset or 3-input combinatorial
function. Low cost of registers ideal for
registers filtering applications.
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ProASIC Routing Resources
ProASIC has 4 distinct classes of routing
resources.

• Four high-speed global paths
• High-performance routing hierarchy
• Corner-to-corner delaylt 4ns (typical)

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Global Routing
ProASIC has flexible global resources.
Accessible from 4 pads. Used for clocks,
sets/resets and other high fanout nets. 4
H-trees. 3.5ns delay. 0.25ns skew Tree
junctions controlled by switch.
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Example of Global Distribution
Unused branches of the global network are
disconnected from the network, saving power.
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High Speed Bus Lines
Bus network designed for processor-based
functionality.
24 Lines 24 Lines 24 Lines 24 Lines 24
Lines 24 Lines 24 Lines 24 Lines 24 Lines
24 Lines 8 Lines
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Local Routing
Efficient Long Lines (1, 2 or 4 Tiles long)
Connection to logic cell inputs
Inputs
Ultra Fast Local Lines to 8 surrounding Tiles
Output
Intrinsic Cell Wire Delay lt 0.5ns (Typical)
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IO Functionality
Individually Selectable 3.3V 2.5V
I/Os 3.3V 33MHz PCI Compliant Individually
Selectable Slew Rate Control 25, 50, 100mA/nsec
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Outline

• Device and Technology
• Architecture
• Beam Tests and Results

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Heavy Ion Test
Device ProASIC A500K050
Foundry/Technology Infineon/0.25 µm
Facility Brookhaven
Ions Br-81, 252.5MeV (LET37MeV-cm2/mg) Cl-35, 210MeV (LET11.45MeV-cm2/mg)
Fluence per Run 107 cm-2
Design 400bits shift register

• Results
• SEL detected, 16.2 lt LETth lt 22.9MeV-cm2/mg.
• SEU cross-section at 16.2MeV-cm2/mg is 9.6 x 10-8
  cm2/bit.
• No detectable FLASH switch upset.

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Heavy Ion Test
Device ProASIC A500K130
Foundry/Technology Infineon/0.25 µm
Facility Berkeley
Ions Ar, Cu, Cr, Xe
Design 240bits twisted ring counter

• Results

Ion LET (MeV-cm2/mg) SEL X-section (cm2/device)
Ar 15 1.8 x 10-7
Cu 30 1.3 x 10-6
Cr 41 1.6 x 10-5
Xe 63 4.9 x 10-5
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Proton Test
Device ProASIC A500K130
Foundry/Technology Infineon/0.25 µm
Facility LLUMC
Neutron Energy 50, 100, 200MeV
Fluence per run 107 p/cm-2
Design 240bits twisted ring counter

• Results
• No SEL

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Configuration Switch SEU
The FLASH switch is intrinsically SEU hard.
DQ/Q lt 3 for LET 100MeV-cm2/mg Total dose
effect can be counteracted by periodically
refreshing the device.
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SEE during Configuration
The switch is susceptible to gate rupture during
configuration (high voltage across thin oxide)
which may limit effectiveness for reconfigurable
payloads.
Configuration not required for conventional FPGA
applications. Peripheral high voltage
(programming) circuits maybe susceptible to
latch-up.
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Conclusions

• ProASIC offers a high-density, re-programmable,
  and non-volatile programmable logic solution to
  high reliability market.
• However, at this moment
• ProASIC is not suitable for space-flight
  application due to its SEL sensitivity at
  moderate LETTH.
• But for avionics, the heavy ion and proton
  testing data show that it is immune to neutrons.