Logical Effort A Method to Optimize Circuit Topology

1
Logical EffortA Method to Optimize Circuit
Topology

• Swarthmore College
• E77 VLSI Design
• Adem Kader
• David Luong
• Mark Piper
• December 6, 2005

2
Current Issues Facing Circuit Designers

• Wanting to optimize circuits for faster
  performance, inexperienced designers often
  encounter
• Simulate-and-Tweak loops
• Incomplete intuition in design process
• Uncertainty in decision-making

3
Logical Effort as a Solution

• Quick method of circuit analysis
• Circuit topology
• Transistor sizing
• Delay estimation
• Easy way to compare multi-stage designs
• Back-of-the-envelope calculation
• Provides intuition of circuit timing
  characteristics in complex circuitry

4
How does it work?

• Assumes RC model of a transistor
• d gh p
• d propagation delay
• gh effort delay
• g logical effort
• h electrical effort Cout/Cin
• p parasitic delay

5
Defining Logical Effort

• Ratio of the input capacitance of the gate to the
  input capacitance of an inverter that can deliver
  the same output current
• Measure of a gate to drive a particular fan-out
  relative to an inverter

6
Visualizing Logical Effort
7
Application of Logical EffortEstimating Delay
Propagation
INVERTER
d g h p
NAND
8
Multi-Stage Design and Logical Effort

• Often circuits are more complicated than an
  inverter or a NAND gate
• Same framework applies with the modification

9
Logical Effort and Transistor Sizing

• Interested in choosing transistor sizing to
  minimize stage and overall delay
• f (min) g(i) h(i) F1/N
• Delay equation becomes

• In the end

10
Application of Transistor Sizing
How do we choose stage capacitances given we want
to minimize propagation delay?
11
Optimal Number of Gates
Path Effort F Optimal N Minimum Delay, D Stage Effort, f
0-5.83 1 1.0-6.8 0-5.8
5.82-22.3 2 6.8-11.4 2.4-4.7
22.3-82.2 3 11.4-16.0 2.8-4.4
82.2-300 4 16.0-20.7 3.0-4.2
300-1090 5 20.7-25.3 3.1-4.1
1090-3920 6 25.3-29.8 3.2-4.0
Rule of thumb is
Note that single gate does not always translate
to minimized delay
12
Example The Implementation Problem
Which do you choose?
13
Using Logical Effort

• Option 1
• Path logic effort G 1 6/3 1 2
• Path Branch Effort B 1
• Path electrical effort H Cout/Cin 8C/C 8
• Path Stage effort F GBH 218 16
• Dmin NF1/NP 3(16)1/3 (141 1)
  33.25 6 13.5

14
Using Logical Effort

• Option 2
• Path logic effort G 1 4/3 5/3 20/9
• Path Branch Effort B 1
• Path electrical effort H Cout/Cin 8C/C 8
• Path Stage effort F GBH 20/918 160/9
• Dmin NF1/NP 3(160/9)1/3 (121 2)
  33.25 5 12.8

15
Using SPICE
16
Example Choosing the Optimal NThe Buffer Problem

• Must drive 64 parallel inverters
• Choose 1, 3, or 5 series inverter stages to drive
  the load?

17
finding optimal of stages
N 5 3 1
f 2.3 4 64
D 16.5 15 65
18
1 inverter
19
3 inverters
20
5 inverters
21
all together
22
Problems with logical effort

• Its only an approximation
• But a good one
• It does not guarantee optimal solution
• but gets quite close
• Chicken and egg problem
• chicken
• Built for speed
• Does not account for power consumption and
  physical size

23
So What Have We Learned?

• Logical Effort
• Provides method to quickly determine speed of
  design topologies for comparison
• Displays changes to parameter tweaking

24
Its so logical!
I agree with stupid ?
now that makes sense!