MonolithIC 3D ICs

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MonolithIC 3D ICs

• November 2012

MonolithIC 3D Inc. , Patents Pending
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Monolithic 3D RC-JLT (Recessed-Channel
Junction-Less Transistor)
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Technology

• Monolithic 3D IC technology is applied
  to producing monolithically stacked low
  leakage Recessed Channel Junction-Less
  Transistors (RC-JLTs).Junction-less (gated
  resistor) transistors are very simple to
  manufacture, and they scale easily to devices
  below 20nm
•  Bulk Device, not surface
•  Fully Depleted channel
•  Simple alternative to FinFET
• Superior contact resistance is achieved with
  the heavier doped top layer. The RCAT
  style transistor structure provides ultra-low
  leakage.Monolithic 3D IC provides a path to
  reduce logic, SOC, and memory costs
  without investing in expensive scaling down.

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RCJLT a monolithic process flow
Using a new wafer, construct dopant regions in
top 100nm and activate at 1000ºC
Oxide
N
100nm
N
Wafer, 700µm
P-
MonolithIC 3D Inc. , Patents Pending
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Implant Hydrogen for Ion-Cut
H
Oxide
N
100nm
N
P-
Wafer, 700µm
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Hydrogen cleave plane for Ion-Cut formed in
donor wafer
Oxide
N
100nm
N
10nm
P-
Wafer, 700µm
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Flip over and bond the donor wafer to the base
(acceptor) wafer
Donor Wafer, 700µm
P-
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
Base Wafer, 700µm
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Perform Ion-Cut Cleave
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Complete Ion-Cut
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Etch Isolation regions as the first step to
define RCAT transistors
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Fill isolation regions (STI-Shallow Trench
Isolation) with Oxide, and CMP
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Etch RCAT Gate Regions
Gate region
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Form Gate Oxide
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Form Gate Electrode
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Add Dielectric and CMP
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Etch Thru-Layer-Via and RCJLT Transistor Contacts
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Fill in Copper
N
100nm
N
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Add more layers monolithically
N
100nm
N
Oxide
N
100nm
N
Oxide
1µ Top Portion of Base (acceptor) Wafer
Base Wafer 700µm
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MonolithIC 3D Inc. Patents Pending
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Benefits for RCJLT

• 2x lower power
• 2x smaller silicon area
• 4x smaller footprint
• Layer to layer interconnect density at close to
  full lithographic resolution and alignment
• Performance of single crystal silicon transistors
  on all layers in the 3D IC
• Scalable scales naturally with
  equipment capability
• Forestalls next gen litho-tool risk
• Also useful as Anti-Fuse FPGA programming
  transistors programmable
• interconnect is 10x-50x smaller lower power
  than SRAM FPGA
• Base logic circuits could be UT-BBOX, FinFET, or
  JLT CMOS logic devices

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RC-JLT flow Summary
Create a layer of Recessed Channel Junction-Less
Transistors (RC-JLTs), a junction-less version of
the RCAT used in DRAMs, by activating dopants at
1000C before wafer bonding to the CMOS
substrate and cleaving, thereby leaving a very
thin doped stack layer from which transistors are
completed, utilizing less than 400C etch and
deposition processes.