MonolithIC 3D ICs

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MonolithIC 3D ICs

• RCAT approach

MonolithIC 3D Inc. , Patents Pending
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3D ICs at a glance

• A 3D Integrated Circuit is a chip that has
  active electronic components stacked on one or
  more layers that are integrated both vertically
  and horizontally forming a single circuit.
• Manufacturing technologies
• Monolithic
• TSV based stacking
• Chip Stacking w/wire bonding

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MonolithIC 3D

• A technology breakthrough allows the fabrication
  of semiconductor devices with multiple thin tiers
  (lt1um) of copper connected active devices
  utilizing conventional fab equipment. MonolithIC
  3D Inc. offers solutions for logic, memory and
  electro-optic technologies, with significant
  benefits for cost, power and operating speed.

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Comparison of Through-Silicon Via (TSV) 3D
Technology and Monolithic 3D Technology

• The semiconductor industry is actively pursuing
  3D Integrated Circuits (3D-ICs) with
  Through-Silicon Via (TSV) technology (Figure 1).
  This can also be called a parallel 3D process.
• As shown in Figure 2, the International
  Technology Roadmap for Semiconductors (ITRS)
  projects TSV pitch remaining in the range of
  several microns, while on-chip interconnect pitch
  is in the range of 100nm.
• The TSV pitch will not reduce appreciably in the
  future due to bonder alignment limitations
  (0.5-1um) and stacked silicon layer thickness
  (6-10um). While the micron-ranged TSV pitches
  may provide enough vertical connections for
  stacking memory atop processors and
  memory-on-memory stacking, they may not be enough
  to significantly mitigate the well-known on-chip
  interconnect problems.
• Monolithic 3D-ICs offer through-silicon
  connections with lt50nm diameter and therefore
  provide 10,000 times the areal density of TSV
  technology.

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Typical TSV process
Figure 1
Processed Top Wafer
Align and bond
Processed Bottom Wafer

• TSV diameter typically 5um
• Limited by alignment accuracy and silicon
  thickness

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Two Types of 3D Technology
3D-TSV Transistors made on separate wafers _at_ high
temp., then thin align bond
Monolithic 3D Transistors made monolithically
atop wiring (_at_ sub-400oC for logic)
TSV pitch gt 1um
TSV pitch 50-100nm
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Reference P. Franzon Tutorial at IEEE 3D-IC
Conference 2011
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Figure 2ITRS Roadmap compared to monolithic 3D
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TSV (parallel) vs. Monolithic (sequential)
Source CEA Leti Semicon West 2012 presentation
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The Monolithic 3D Challenge

• Once copper or aluminum is added on for bottom
  layer interconnect, the process temperatures need
  to be limited to less than 400ºC !!!
• Forming single crystal silicon require 1,000ºC
• Forming transistors in single crystal silicon
  require 800ºC
• The TSV solution overcame the temperature
  challenge by forming the second tier transistors
  on an independent wafer, then thinning and
  bonding it over the bottom wafer (parallel)
• The limitations
• Wafer to wafer misalignment 1µ
• Overlaying wafer could not be thinned to less
  than 50µ

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The Monolithic 3D Innovation

• Utilize Ion-Cut (Smart-Cut) to transfer a thin
  (lt100nm) single crystal layer on top of the
  bottom (base) wafer
• Form the cut at less than 400ºC
• Use co-implant
• Use mechanical assisted cleaving
• Form the bonding at less than 400ºC
• See details at Low Temperature Cleaving, Low
  Temperature Wafer Direct Bonding
• Split the transistor processing to two portions
• High temperature process portion (ion implant and
  activation) to be done before the Ion-Cut
• Low temperature (lt400C) process portion (etch
  and deposition) to be done after layer transfer
• See details in the following slides

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Monolithic 3D ICs

• Using SmartCut technology - the ion cutting
  process that Soitec uses to make SOI wafers for
  AMD and IBM (million of wafers had utilized the
  process over the last 20 years) - to stack up
  consecutive layers of active silicon (bond first
  and then cut). Soitecs Smart Cut Patented Flow

Soitecs fundamental patent US 5,374,564 expired
Sep. 15, 2012
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Monolithic 3D ICs

• Ion cutting the key idea is that if you implant
  a thin layer of H ions into a single crystal of
  silicon, the ions will weaken the bonds between
  the neighboring silicon atoms, creating a
  fracture plane (Figure 3). Judicious force will
  then precisely break the wafer at the plane of
  the H implant, allowing you to in effect peel
  off very thin layer. This technique is currently
  being used to produce the most advanced
  transistors (Fully Depleted SOI, UTBB transistors
  Ultra Thin Body and BOX), forming
  monocrystalline silicon layers that are less than
  10nm thick.

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Figure 3Using ion-cutting to place a thin layer
of monocrystalline silicon above a processed
(transistors and metallization) base wafer
Cleave using lt400oC anneal or sideways
mechanical force. CMP.
Hydrogen implant of top layer
Flip top layer and bond to bottom layer
Oxide
p- Si
Top layer
Oxide
p- Si
H
p- Si
H
p- Si
Oxide
Oxide
Oxide
Oxide
Oxide
Bottom layer
Similar process (bulk-to-bulk) used for
manufacturing all SOI wafers today
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MonolithIC 3D The RCAT path

• The Recessed Channel Array Transistor (RCAT) fits
  very nicely into the hot-cold process flow
  partition
• RCAT is the transistor used in commercial DRAM as
  its 3D channel overcomes the short channel effect
  
• Used in DRAM production _at_ 90nm, 60nm, 50nm nodes
• Higher capacitance, but less leakage, same drive
  current
• The following slides present the flow to process
  an RCAT without exceeding the 400ºC temperature
  limit

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RCAT a monolithic process flow
Using a new wafer, construct dopant regions in
top 100nm and activate at 1000º C
Oxide
P-
100nm
N
Wafer, 700µm
P-
MonolithIC 3D Inc. , Patents Pending
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Implant Hydrogen for Ion-Cut
H
Oxide
P-
100nm
N
P-
Wafer, 700µm
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Hydrogen cleave plane for Ion-Cut formed in
donor wafer
Oxide
P-
100nm
N
10nm
P-
Wafer, 700µm
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Flip over and bond the donor wafer to the base
(acceptor) wafer
Donor Wafer, 700µm
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
Base Wafer, 700µm
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Perform Ion-Cut Cleave
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Complete Ion-Cut
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Etch Isolation regions as the first step to
define RCAT transistors
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Fill isolation regions (STI-Shallow Trench
Isolation) with Oxide, and CMP
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Etch RCAT Gate Regions
Gate region
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Form Gate Oxide
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Form Gate Electrode
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Add Dielectric and CMP
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Etch Thru-Layer-Via and RCAT Transistor Contacts
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Fill in Copper
N
100nm
P-
Oxide
1µ Top Portion of Base Wafer
MonolithIC 3D Inc. Patents Pending
Base Wafer 700µm
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Add more layers monolithically
N
100nm
P-
Oxide
N
100nm
P-
Oxide
1µ Top Portion of Base (acceptor) Wafer
Base Wafer 700µm
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MonolithIC 3D Inc. Patents Pending