RT Level Design

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RT Level Design

• RT level design
• Taking a high level description of a design
• Partitioning
• Coming up with an architecture
• Designing the bussing structure
• Describing and implementing various components of
  the architecture
• Steps in RT level design
• Control/Data Partitioning
• Data Part Design
• Control Part Design

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RT Level Design
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Control/Data Partitioning
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Control/Data Partitioning
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Data Part
Data Part
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Data Part
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Output Signals Going to the control part,
provide flags and status of the data
Data Part
module DataPath (DataInput, DataOutput, Flags,
Opcodes, ControlSignals) input 150
DataInputs output 150 DataOutputs output
Flags, ... output Opcodes, ... input
ControlSignals, ... // instantiation of data
components // ... // interconnection of data
components // bussing specification endmodule
Control Signals Inputs to data part, sent to the
data components and busses

• DataPath Module

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Data Part
Data Component Shows how the component uses its
input control signals to perform various
operations on its data inputs
module DataComponent (DataIn, DataOut,
ControlSignals) input 70 DataIn output
70 DataOut input ControlSignals //
Depending on ControlSignals // Operate on
DataIn and // Produce DataOut endmodule

• Partial Verilog Code of a Data Component

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Control Part
Control Part
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Control Part
Makes decisions as to when and what control
signals to issue depending on its state.
Consists of one or more state machines to keep
the state of the circuit.
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Control Part
module ControlUnit (Flags, Opcodes,
ExternalControls, ControlSignals) input
Flags, ... input Opcodes, ... input
ExternalControls, ... output ControlSignals //
Based on inputs decide // What control
signals to issue, // and what next state to
take endmodule
Takes control inputs from the Data Part

• Outline of a Controller

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Sequential Multiplier
An add-and-shift Sequential Multiplier
Multiplication begins with the start pulse.
When both bytes are outputed.
For the most-significant byte
An 8-bit bidirectional I/O for inputing its
8-bit operands and outputing its 16-bit output
one byte at a time.

• Multiplier Block Diagram

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Sequential Multiplier
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Shift-and-add Multiplication Process
Shift-and-add Multiplication Process
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Shift-and-add Multiplication Process
Depending on bit i of operand A, either operand B
is added to the collected partial result and
then shifted to the right (when bit i is 1)
Or (when bit i is 0) the collected partial
result is shifted one place to the right without
being added to B.

• Manual Binary Multiplication

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Shift-and-add Multiplication Process

• Hardware Oriented Multiplication Process

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Shift-and-add Multiplication Process
Because A0 is 1, the partial sum of B P is
calculated.

• Hardware Oriented Multiplication Process
  (Continued)

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Shift-and-add Multiplication Process
Because A0 is 0, 0000 P is calculated
The right most bit of which is shifted into
A, and the rest replace P

• Hardware Oriented Multiplication Process
  (Continued)

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Shift-and-add Multiplication Process
The least significant 4 bits of the
multiplication result become available in A and
the most-significant bits in P.

• Hardware Oriented Multiplication Process
  (Continued)

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Sequential Multiplier Design
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Sequential Multiplier Design
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Control Data Partitioning
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Control Data Partitioning
Data part consists of registers, logic units,
and their interconnecting buses.
On the rising edge of the system clock, the
controller goes into a new state.

• Datapath and Controller

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Multiplier Datapath
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Multiplier Datapath
Selects carry-out from the adder or 0
depending on the value of sel_sum
Adder
Multiplexer
8-bit Registers
8-bit Shift Register
Tri-state Buffers

• Multiplier Block Diagram

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Datapath Description
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Datapath Description
module datapath ( input clk, clr_P, load_P,
load_B, msb_out, lsb_out, sel_sum,
load_A, shift_A, inout 70 data, output A0
) wire 70 sum, ShiftAdd reg 70
A, B, P wire co .........................
...... ...............................

• Datapath Verilog Code

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Datapath Description
Represents register B
always _at_( posedge clk ) if (load_B) B lt data
always _at_( posedge clk ) if (load_P) P lt
cosel_sum, ShiftAdd71 assign co,
sum P B always _at_( posedge clk )
case ( load_A, shift_A ) 2'b01 A
lt ShiftAdd0, A71 2'b10 A lt
data default A lt A endcase
Represents register P for the partial result
Represents the 8-bit adder
Shifts A contents
Loads A with data

• Datapath Verilog Code (Continued)

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Datapath Description
............................... assign A0
A0 assign ShiftAdd clr_P ? 8'h0
( sel_sum ? P sum ) assign
data lsb_out ? A 8'hzz assign data
msb_out ? P 8'hzz endmodule
Multiplexer for selection of sum or P
2 sets of tri-state buffers driving the
bidirectional data bus of the datapath

• Datapath Verilog Code (Continued)

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Multiplier Controller
Multiplier Controller
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Datapath Description
The multiplier controller is a finite state
machine that has 2 starting states, 8
multiplication states, and 2 ending states.
The multiplier waits for start while loading A
define idle 4'b0000 define init
4'b0001 define m1 4'b0010 define m2
4'b0011 define m3 4'b0100 define m4
4'b0101 define m5 4'b0110 define m6
4'b0111 define m7 4'b1000 define
m8 4'b1001 define rslt1
4'b1010 define rslt2 4'b1011
Multiplier loads B
States and their binary assignments
The 2 halves of the result are put on databus.

• Multiplier Control States

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Multiplier Controller
Declares signals that connect to datapath ports
module controller ( input clk, start, A0,
output reg clr_P, load_P, load_B, msb_out,
lsb_out, sel_sum, output reg load_A,
Shift_A, done) reg 30 current
always _at_ ( negedge clk ) begin clr_P 0
load_P 0 load_B 0 msb_out 0 lsb_out
0 sel_sum 0 load_A 0 Shift_A 0
done 0 ..................................
always block to issue control signals and
make state transitions
Eliminating unwanted latches that may
be generated by a synthesis tool for these
outputs.

• Verilog Code of Controller

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Multiplier Controller
The currently active state of the machine
case ( current ) idle
if (start) begin current lt
idle done 1 end
else begin current lt init
load_A 1 clr_P 1 load_P 1
end init begin
current lt m1 load_B 1 end
To clear the P register
To Load A

• Verilog Code of Controller (Continued)

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Multiplier Controller
............................... m1,
m2, m3, m4, m5, m6, m6, m7, m8
begin current lt current
1 Shift_A 1 load_P 1 if
(A0) sel_sum 1 end
...............................
Shifting A
Loading P
Asserting sel_sum

• Verilog Code of Controller (Continued)

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Multiplier Controller
In the result states, lsb_out and msb_out are
asserted in two consecutive clocks in order to
put A and P on the data bus respectively.
rslt1 begin current lt
rslt2 lsb_out 1 end
rslt2 begin current
lt idle msb_out 1 end
default current lt idle endcase
end endmodule

• Verilog Code of Controller (Continued)

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Top-Level Code of the Multiplier
Top-Level Code of the Multiplier
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Top-Level Code of the Multiplier
module Multiplier ( input clk, start,
inout 70 databus, output
lsb_out, msb_out, done ) wire clr_P, load_P,
load_B, msb_out, lsb_out, sel_sum, load_A,
Shift_A datapath dpu( clk, clr_P, load_P,
load_B, msb_out, lsb_out,
sel_sum, load_A, Shift_A, databus,
A0 ) controller cu( clk, start, A0, clr_P,
load_P, load_B, msb_out, lsb_out, sel_sum,
load_A, Shift_A, done ) endmodule
Datapath and controller modules are instantiated.

• Top-Level Multiplier Code

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Multiplier Testing
Multiplier Testing
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Multiplier Testing
timescale 1ns/100ps module test_multiplier
reg clk, start, error wire 70 databus
wire lsb_out, msb_out, done reg 70
mem102, mem202 reg 70 im_data,
opnd1, opnd2 reg 150 expected_result,
multiplier_result integer indx
...............................
...............................
An auto-check interactive testbench for the
sequential multiplier
A bidirectional bus, declared as wire for reading
Declared for writing to the bidirectional databus
What is calculated in the testbench
The result read from the multiplier

• Multiplier Testbench Outline

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Multiplier Testing
Read data files data1.dat and data2.dat and
apply data to databus
...............................
Multiplier uut ( clk, start, databus, lsb_out,
msb_out, done ) initial begin
Apply_data ... end //Figure 8.11 initial
begin Apply_Start ... end //Figure 8.12
initial begin Expected_Result... end
//Figure8.13 always _at_(posedge clk) begin
Actual_Result ... end // Figure 8.14 always
_at_(posedge clk) begin Compare_Results...end //
Figure 8.15 always 50 clk clk assign
databusim_data endmodule
Apply start to start multiplication
Calculate the expected result
Wait for multiplication to complete, and collect
the calculated result
Compare expected and calculated results and
issue error if they do not match
Applies three rounds of test to the Multiplier
module. In each round, data is applied to the
module under test and results are read and
compared with the expected results.
Above tasks are timed independently, at the same
time, an always block generates a periodic signal
on clk that clocks the multiplier.

• Multiplier Testbench Outline

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Multiplier Testing