Timing Model Reduction for Hierarchical Timing Analysis

1
Timing Model Reduction for Hierarchical Timing
Analysis

• Shuo Zhou
• Synopsys
• November 7, 2006

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Outline

• Static Timing Analysis in Design Flow
• Hierarchical timing analysis
• Proposed Techniques
• Iterative timing model reduction algorithm based
  on a biclique-star replacement technique.
• Experimental Results
• Conclusions

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Static Timing Analysis in Design Flow

• Static Timer is integrated in each stage.
• Need efficient static timer.

4
Hierarchical Timing Analysis

• Hierarchical timing analysis is essential for
  hierarchical design.
• Consider circuits inside the blocks to be fixed.
• Complexity O(n) n is edges in timing models.

gates
gates
gates
Partition Design into Blocks
Characterize Blocks into Timing Models
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Problem Statement

• Timing model minimization for hierarchical timing
  analysis
• Given a hierarchical block, construct an abstract
  timing model with minimal number of edges that
  covers the longest and shortest path delays of
  each pair of input and output in the block.

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Previous Works

• Transform timing graph Visweswariah ICCAD99,
  Moon DAC02.
• Perform serial/parallel edge merging.
• Represent delay matrix with minimal number of
  edges.
• Optimal realization of a distance matrix Hakimi
  Quart. Appl. Math. 22 (1964), Chung
  http//www.math.ucsd.edu/fan.
• Biclique-star replacement for bicliques with unit
  edge delay Feder Symp. on Theoretical Aspects of
  Computer Science (2003).

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Terminologies Bipartite Timing Model

• G B, D, E
• Input set B, output set D, and edge set E
• Longest and shortest delays.

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path 1-gt4-gt5-gt7-gt8-gt10
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Delay matrix

• Element on row i col j is delay from input i to
  output j, ? for disconnected input i and output
  j.
• Row i implies input delay vector di,j di,j
  from input i.

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Star

• Gs (Bs, Ds, s, Es)
• Bs input set, Ds output set, center vertex s.
• Edges (i,s) and (s,j).

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Biclique-Star Replacement

• Basic idea match various input delay vectors to
  a pattern and cover each input delay vector by
  one edge plus the pattern.

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Biclique edge 9
star edge 6
2
1
4
4
1
3
0
2
4
3
3
1
4
s
2
5
5
2
5
4
2
4
5
6
3
6
6
3
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Bipartite Timing Model Reduction
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Delay Vector Subtraction

• Input delay vector subtraction Sub(Ia, Ib)
• Distance vector V(Ia,Ib) ?jIa,Ib da,j db,j
  j ?1..c
• Input vectors Ia, Ib share a pattern if all
  ?jIa,Ib are equal.

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Biclique Expansion for Replacements

• Choose an input delay vector as the pattern
  vector.
• Expand the biclique of the pattern vector by
  covering as many as possible input vectors.
• Replace the biclique by a star.
• Biclique Expansion (G, Ia, Gc)
• Add edges (a,j) to biclique Gc
• For each input vector Ii
• Vector subtraction Sub(Ii,Ia)
• If all ?jIi,Ia ?0Ii,Ia add edges (i, j) to
  Gc.
• Biclique-star Replacement (Gc,Ia,Gs)
• Add inputs, outputs, center vertex s, and edges
  (i,s), (s,j) to Gs
• da,s 0, ds,j Ia,j
• For each edge (i,s) in Gs
• di,s ?0Ii,Ia

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Replace
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Dont Care Edges

• Edge (i,j) is a dont care edge in a biclique
  star replacement if path delay di,s ds,j lt di,j.

Replace
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Biclique Expansion with Dont Cares

• Choice try each ? in distance vector as di,s.
• For d3,s ?
• di,j is covered if di,s ds,j di,j, i.e., ?j
  ?.
• di,j is a dont care edge if ?j gt ?.
• Output j has to be removed if ?j lt ?.

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edges covered decreases by 1
edges covered increases by 2
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Biclique Expansion and Replacement with Dont
Cares

• Biclique Expansion with Dont Cares (G, Ia, Gc)
• Add edges (a,j) to Gc
• For each input vector Ii
• Vector subtraction Sub(Ii,Ip)
• For each ?j in the distance vector
• For each ?k in distance vector
• if ?k ?j covered
• else if ?k lt ?j removed edges to output k
• If maximum (covered - removed of ?j )gt 1
• For each ?k in distance vector
• if ?k ? ?j Add edge (i,k) to Gc
• else remove output k and edges to k.
• Replacement with Dont Cares (Gc, Ia, Gs)
• Add inputs, outputs, center vertex s, and edges
  to Gs
• da,s 0, ds,j Ia,j
• For each edge (i,s) in Gs
• di,s min(?Ii,Ia ).

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Replace
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Bipartite Timing Model Reduction
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Star Graph to Bipartite Graph Transformation
Split s1,s2
Recover Stars
6
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Correctness

• G the bipartite timing model before the
  reduction.
• G' the timing model after the reduction.
• Edge delay di,j of any connected input i and
  output j in G is covered by the longest path
  delay di,j' from input i to output j in G' after
  the reduction.

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Experimental Results

• Test cases
• Block 1 8499 inputs, 16885 outputs, and 138,360
  edges
• Block 2 4260 inputs, 7728 outputs and 103,414
  edges
• EG-- edges in original timing graph of the
  block.
• EB--edges in bipartite timing model.
• Em--edges after timing model reduction.
• Reduction rG (EG Em)/ EG.
• Reduction rB (EB Em)/ EB.

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• di,j di,j lt Err_bound, where di,j and di,j
  are delays from input i to output j before and
  after the reduction.

Block1 EG 138,360, EB 262,491 Block1 EG 138,360, EB 262,491 Block1 EG 138,360, EB 262,491 Block1 EG 138,360, EB 262,491
Err_bound (ns) Em rG rB
0 249,032 -80.0 5.1
0.1 41,696 69.9 84.1
1.0 36,980 73.3 85.9
10.0 35,981 74.0 86.3
100.0 36,169 73.9 86.2
Buffer?1 delay 1.34ns.
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Block2 EG 103,414, EB 465,190 Block2 EG 103,414, EB 465,190 Block2 EG 103,414, EB 465,190 Block2 EG 103,414, EB 465,190
Err_bound (ns) Em rG rB
0 397,384 -284.3 14.6
0.01 49,613 52.0 89.3
0.10 29,477 71.5 93.7
1.0 21,192 79.5 95.4
10.0 20,262 80.4 95.6
Buffer ?1 delay 0.74ns.
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Conclusions

• We propose a biclique-star replacement technique
  and develop an iterative timing model reduction
  algorithm based the proposed technique.
• By allowing reasonable error bounds, the
  experimental results show that the proposed
  algorithm can effectively reduce the number of
  edges in the timing model.

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Thanks!
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References

• C.W. Moon, H.Kriplani, and K.P. Belkhale,
  Timing model extraction of hierarchical blocks
  by graph reduction, in DAC02, 152-157.
• C. Visweswariah and A.R. Conn, Formulation of
  static circuit optimization with reduced size,
  degeneracy and redundancy by timing graph
  manipulation, in ICCAD99, 244-251.
• S. L. Hakimi and S. S. Yau. Distance matrix of a
  graph and its realizability. Quart. Appl. Math.
  22 (1964), 305317.
• F. Chung, M. Garrett, R. Graham, and D.
  Shallcross. Distance realization problems with
  applications to internet tomography.
  http//www.math.ucsd.edu/fan.
• T. Feder and A. Meyerson and R. Motwani and L. O'
  Callaghan and R. Panigrahy, Representing graph
  metrics with fewest edges. in Proc. of Symp. on
  Theoretical Aspects of Computer Science (2003),
  355--366.